root/lj_asm_mips.h

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INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. ra_hintalloc
  2. ra_alloc1z
  3. ra_alloc2
  4. asm_sparejump_setup
  5. asm_exitstub_setup
  6. asm_guard
  7. noconflict
  8. asm_fuseabase
  9. asm_fuseahuref
  10. asm_fusexref
  11. asm_gencall
  12. asm_setupresult
  13. asm_callx
  14. asm_callround
  15. asm_retf
  16. asm_tointg
  17. asm_tobit
  18. asm_tointg
  19. asm_tobit
  20. asm_conv
  21. asm_strto
  22. asm_tvstore64
  23. asm_tvptr
  24. asm_aref
  25. asm_href
  26. asm_hrefk
  27. asm_uref
  28. asm_fref
  29. asm_strref
  30. asm_fxloadins
  31. asm_fxstoreins
  32. asm_fload
  33. asm_fstore
  34. asm_xload
  35. asm_xstore_
  36. asm_ahuvload
  37. asm_ahustore
  38. asm_sload
  39. asm_cnew
  40. asm_tbar
  41. asm_obar
  42. asm_fparith
  43. asm_fpunary
  44. asm_fpmath
  45. asm_add
  46. asm_sub
  47. asm_mul
  48. asm_mod
  49. asm_pow
  50. asm_div
  51. asm_neg
  52. asm_abs
  53. asm_arithov
  54. asm_mulov
  55. asm_add64
  56. asm_sub64
  57. asm_neg64
  58. asm_bnot
  59. asm_bswap
  60. asm_bitop
  61. asm_bitshift
  62. asm_bror
  63. asm_sfpmin_max
  64. asm_min_max
  65. asm_sfpcomp
  66. asm_comp
  67. asm_equal
  68. asm_comp64
  69. asm_comp64eq
  70. asm_hiop
  71. asm_prof
  72. asm_stack_check
  73. asm_stack_restore
  74. asm_gc_check
  75. asm_loop_fixup
  76. asm_head_root_base
  77. asm_head_side_base
  78. asm_tail_fixup
  79. asm_tail_prep
  80. asm_setup_call_slots
  81. asm_setup_target
  82. lj_asm_patchexit

   1 /*
   2 ** MIPS IR assembler (SSA IR -> machine code).
   3 ** Copyright (C) 2005-2017 Mike Pall. See Copyright Notice in luajit.h
   4 */
   5 
   6 /* -- Register allocator extensions --------------------------------------- */
   7 
   8 /* Allocate a register with a hint. */
   9 static Reg ra_hintalloc(ASMState *as, IRRef ref, Reg hint, RegSet allow)
  10 {
  11   Reg r = IR(ref)->r;
  12   if (ra_noreg(r)) {
  13     if (!ra_hashint(r) && !iscrossref(as, ref))
  14       ra_sethint(IR(ref)->r, hint);  /* Propagate register hint. */
  15     r = ra_allocref(as, ref, allow);
  16   }
  17   ra_noweak(as, r);
  18   return r;
  19 }
  20 
  21 /* Allocate a register or RID_ZERO. */
  22 static Reg ra_alloc1z(ASMState *as, IRRef ref, RegSet allow)
  23 {
  24   Reg r = IR(ref)->r;
  25   if (ra_noreg(r)) {
  26     if (!(allow & RSET_FPR) && irref_isk(ref) && get_kval(IR(ref)) == 0)
  27       return RID_ZERO;
  28     r = ra_allocref(as, ref, allow);
  29   } else {
  30     ra_noweak(as, r);
  31   }
  32   return r;
  33 }
  34 
  35 /* Allocate two source registers for three-operand instructions. */
  36 static Reg ra_alloc2(ASMState *as, IRIns *ir, RegSet allow)
  37 {
  38   IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
  39   Reg left = irl->r, right = irr->r;
  40   if (ra_hasreg(left)) {
  41     ra_noweak(as, left);
  42     if (ra_noreg(right))
  43       right = ra_alloc1z(as, ir->op2, rset_exclude(allow, left));
  44     else
  45       ra_noweak(as, right);
  46   } else if (ra_hasreg(right)) {
  47     ra_noweak(as, right);
  48     left = ra_alloc1z(as, ir->op1, rset_exclude(allow, right));
  49   } else if (ra_hashint(right)) {
  50     right = ra_alloc1z(as, ir->op2, allow);
  51     left = ra_alloc1z(as, ir->op1, rset_exclude(allow, right));
  52   } else {
  53     left = ra_alloc1z(as, ir->op1, allow);
  54     right = ra_alloc1z(as, ir->op2, rset_exclude(allow, left));
  55   }
  56   return left | (right << 8);
  57 }
  58 
  59 /* -- Guard handling ------------------------------------------------------ */
  60 
  61 /* Need some spare long-range jump slots, for out-of-range branches. */
  62 #define MIPS_SPAREJUMP          4
  63 
  64 /* Setup spare long-range jump slots per mcarea. */
  65 static void asm_sparejump_setup(ASMState *as)
  66 {
  67   MCode *mxp = as->mcbot;
  68   if (((uintptr_t)mxp & (LJ_PAGESIZE-1)) == sizeof(MCLink)) {
  69     lua_assert(MIPSI_NOP == 0);
  70     memset(mxp, 0, MIPS_SPAREJUMP*2*sizeof(MCode));
  71     mxp += MIPS_SPAREJUMP*2;
  72     lua_assert(mxp < as->mctop);
  73     lj_mcode_sync(as->mcbot, mxp);
  74     lj_mcode_commitbot(as->J, mxp);
  75     as->mcbot = mxp;
  76     as->mclim = as->mcbot + MCLIM_REDZONE;
  77   }
  78 }
  79 
  80 /* Setup exit stub after the end of each trace. */
  81 static void asm_exitstub_setup(ASMState *as)
  82 {
  83   MCode *mxp = as->mctop;
  84   /* sw TMP, 0(sp); j ->vm_exit_handler; li TMP, traceno */
  85   *--mxp = MIPSI_LI|MIPSF_T(RID_TMP)|as->T->traceno;
  86   *--mxp = MIPSI_J|((((uintptr_t)(void *)lj_vm_exit_handler)>>2)&0x03ffffffu);
  87   lua_assert(((uintptr_t)mxp ^ (uintptr_t)(void *)lj_vm_exit_handler)>>28 == 0);
  88   *--mxp = MIPSI_SW|MIPSF_T(RID_TMP)|MIPSF_S(RID_SP)|0;
  89   as->mctop = mxp;
  90 }
  91 
  92 /* Keep this in-sync with exitstub_trace_addr(). */
  93 #define asm_exitstub_addr(as)   ((as)->mctop)
  94 
  95 /* Emit conditional branch to exit for guard. */
  96 static void asm_guard(ASMState *as, MIPSIns mi, Reg rs, Reg rt)
  97 {
  98   MCode *target = asm_exitstub_addr(as);
  99   MCode *p = as->mcp;
 100   if (LJ_UNLIKELY(p == as->invmcp)) {
 101     as->invmcp = NULL;
 102     as->loopinv = 1;
 103     as->mcp = p+1;
 104     mi = mi ^ ((mi>>28) == 1 ? 0x04000000u : 0x00010000u);  /* Invert cond. */
 105     target = p;  /* Patch target later in asm_loop_fixup. */
 106   }
 107   emit_ti(as, MIPSI_LI, RID_TMP, as->snapno);
 108   emit_branch(as, mi, rs, rt, target);
 109 }
 110 
 111 /* -- Operand fusion ------------------------------------------------------ */
 112 
 113 /* Limit linear search to this distance. Avoids O(n^2) behavior. */
 114 #define CONFLICT_SEARCH_LIM     31
 115 
 116 /* Check if there's no conflicting instruction between curins and ref. */
 117 static int noconflict(ASMState *as, IRRef ref, IROp conflict)
 118 {
 119   IRIns *ir = as->ir;
 120   IRRef i = as->curins;
 121   if (i > ref + CONFLICT_SEARCH_LIM)
 122     return 0;  /* Give up, ref is too far away. */
 123   while (--i > ref)
 124     if (ir[i].o == conflict)
 125       return 0;  /* Conflict found. */
 126   return 1;  /* Ok, no conflict. */
 127 }
 128 
 129 /* Fuse the array base of colocated arrays. */
 130 static int32_t asm_fuseabase(ASMState *as, IRRef ref)
 131 {
 132   IRIns *ir = IR(ref);
 133   if (ir->o == IR_TNEW && ir->op1 <= LJ_MAX_COLOSIZE &&
 134       !neverfuse(as) && noconflict(as, ref, IR_NEWREF))
 135     return (int32_t)sizeof(GCtab);
 136   return 0;
 137 }
 138 
 139 /* Fuse array/hash/upvalue reference into register+offset operand. */
 140 static Reg asm_fuseahuref(ASMState *as, IRRef ref, int32_t *ofsp, RegSet allow)
 141 {
 142   IRIns *ir = IR(ref);
 143   if (ra_noreg(ir->r)) {
 144     if (ir->o == IR_AREF) {
 145       if (mayfuse(as, ref)) {
 146         if (irref_isk(ir->op2)) {
 147           IRRef tab = IR(ir->op1)->op1;
 148           int32_t ofs = asm_fuseabase(as, tab);
 149           IRRef refa = ofs ? tab : ir->op1;
 150           ofs += 8*IR(ir->op2)->i;
 151           if (checki16(ofs)) {
 152             *ofsp = ofs;
 153             return ra_alloc1(as, refa, allow);
 154           }
 155         }
 156       }
 157     } else if (ir->o == IR_HREFK) {
 158       if (mayfuse(as, ref)) {
 159         int32_t ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
 160         if (checki16(ofs)) {
 161           *ofsp = ofs;
 162           return ra_alloc1(as, ir->op1, allow);
 163         }
 164       }
 165     } else if (ir->o == IR_UREFC) {
 166       if (irref_isk(ir->op1)) {
 167         GCfunc *fn = ir_kfunc(IR(ir->op1));
 168         intptr_t ofs = (intptr_t)&gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.tv;
 169         intptr_t jgl = (intptr_t)J2G(as->J);
 170         if ((uintptr_t)(ofs-jgl) < 65536) {
 171           *ofsp = ofs-jgl-32768;
 172           return RID_JGL;
 173         } else {
 174           *ofsp = (int16_t)ofs;
 175           return ra_allock(as, ofs-(int16_t)ofs, allow);
 176         }
 177       }
 178     }
 179   }
 180   *ofsp = 0;
 181   return ra_alloc1(as, ref, allow);
 182 }
 183 
 184 /* Fuse XLOAD/XSTORE reference into load/store operand. */
 185 static void asm_fusexref(ASMState *as, MIPSIns mi, Reg rt, IRRef ref,
 186                          RegSet allow, int32_t ofs)
 187 {
 188   IRIns *ir = IR(ref);
 189   Reg base;
 190   if (ra_noreg(ir->r) && canfuse(as, ir)) {
 191     if (ir->o == IR_ADD) {
 192       intptr_t ofs2;
 193       if (irref_isk(ir->op2) && (ofs2 = ofs + get_kval(IR(ir->op2)),
 194                                  checki16(ofs2))) {
 195         ref = ir->op1;
 196         ofs = (int32_t)ofs2;
 197       }
 198     } else if (ir->o == IR_STRREF) {
 199       intptr_t ofs2 = 65536;
 200       lua_assert(ofs == 0);
 201       ofs = (int32_t)sizeof(GCstr);
 202       if (irref_isk(ir->op2)) {
 203         ofs2 = ofs + get_kval(IR(ir->op2));
 204         ref = ir->op1;
 205       } else if (irref_isk(ir->op1)) {
 206         ofs2 = ofs + get_kval(IR(ir->op1));
 207         ref = ir->op2;
 208       }
 209       if (!checki16(ofs2)) {
 210         /* NYI: Fuse ADD with constant. */
 211         Reg right, left = ra_alloc2(as, ir, allow);
 212         right = (left >> 8); left &= 255;
 213         emit_hsi(as, mi, rt, RID_TMP, ofs);
 214         emit_dst(as, MIPSI_AADDU, RID_TMP, left, right);
 215         return;
 216       }
 217       ofs = ofs2;
 218     }
 219   }
 220   base = ra_alloc1(as, ref, allow);
 221   emit_hsi(as, mi, rt, base, ofs);
 222 }
 223 
 224 /* -- Calls --------------------------------------------------------------- */
 225 
 226 /* Generate a call to a C function. */
 227 static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
 228 {
 229   uint32_t n, nargs = CCI_XNARGS(ci);
 230   int32_t ofs = LJ_32 ? 16 : 0;
 231 #if LJ_SOFTFP
 232   Reg gpr = REGARG_FIRSTGPR;
 233 #else
 234   Reg gpr, fpr = REGARG_FIRSTFPR;
 235 #endif
 236   if ((void *)ci->func)
 237     emit_call(as, (void *)ci->func, 1);
 238 #if !LJ_SOFTFP
 239   for (gpr = REGARG_FIRSTGPR; gpr <= REGARG_LASTGPR; gpr++)
 240     as->cost[gpr] = REGCOST(~0u, ASMREF_L);
 241   gpr = REGARG_FIRSTGPR;
 242 #endif
 243   for (n = 0; n < nargs; n++) {  /* Setup args. */
 244     IRRef ref = args[n];
 245     if (ref) {
 246       IRIns *ir = IR(ref);
 247 #if !LJ_SOFTFP
 248       if (irt_isfp(ir->t) && fpr <= REGARG_LASTFPR &&
 249           !(ci->flags & CCI_VARARG)) {
 250         lua_assert(rset_test(as->freeset, fpr));  /* Already evicted. */
 251         ra_leftov(as, fpr, ref);
 252         fpr += LJ_32 ? 2 : 1;
 253         gpr += (LJ_32 && irt_isnum(ir->t)) ? 2 : 1;
 254       } else
 255 #endif
 256       {
 257 #if LJ_32 && !LJ_SOFTFP
 258         fpr = REGARG_LASTFPR+1;
 259 #endif
 260         if (LJ_32 && irt_isnum(ir->t)) gpr = (gpr+1) & ~1;
 261         if (gpr <= REGARG_LASTGPR) {
 262           lua_assert(rset_test(as->freeset, gpr));  /* Already evicted. */
 263 #if !LJ_SOFTFP
 264           if (irt_isfp(ir->t)) {
 265             RegSet of = as->freeset;
 266             Reg r;
 267             /* Workaround to protect argument GPRs from being used for remat. */
 268             as->freeset &= ~RSET_RANGE(REGARG_FIRSTGPR, REGARG_LASTGPR+1);
 269             r = ra_alloc1(as, ref, RSET_FPR);
 270             as->freeset |= (of & RSET_RANGE(REGARG_FIRSTGPR, REGARG_LASTGPR+1));
 271             if (irt_isnum(ir->t)) {
 272 #if LJ_32
 273               emit_tg(as, MIPSI_MFC1, gpr+(LJ_BE?0:1), r+1);
 274               emit_tg(as, MIPSI_MFC1, gpr+(LJ_BE?1:0), r);
 275               lua_assert(rset_test(as->freeset, gpr+1));  /* Already evicted. */
 276               gpr += 2;
 277 #else
 278               emit_tg(as, MIPSI_DMFC1, gpr, r);
 279               gpr++; fpr++;
 280 #endif
 281             } else if (irt_isfloat(ir->t)) {
 282               emit_tg(as, MIPSI_MFC1, gpr, r);
 283               gpr++;
 284 #if LJ_64
 285               fpr++;
 286 #endif
 287             }
 288           } else
 289 #endif
 290           {
 291             ra_leftov(as, gpr, ref);
 292             gpr++;
 293 #if LJ_64 && !LJ_SOFTFP
 294             fpr++;
 295 #endif
 296           }
 297         } else {
 298           Reg r = ra_alloc1z(as, ref, !LJ_SOFTFP && irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
 299 #if LJ_32
 300           if (irt_isnum(ir->t)) ofs = (ofs + 4) & ~4;
 301           emit_spstore(as, ir, r, ofs);
 302           ofs += irt_isnum(ir->t) ? 8 : 4;
 303 #else
 304           emit_spstore(as, ir, r, ofs + ((LJ_BE && !irt_isfp(ir->t) && !irt_is64(ir->t)) ? 4 : 0));
 305           ofs += 8;
 306 #endif
 307         }
 308       }
 309     } else {
 310 #if !LJ_SOFTFP
 311       fpr = REGARG_LASTFPR+1;
 312 #endif
 313       if (gpr <= REGARG_LASTGPR) {
 314         gpr++;
 315 #if LJ_64 && !LJ_SOFTFP
 316         fpr++;
 317 #endif
 318       } else {
 319         ofs += LJ_32 ? 4 : 8;
 320       }
 321     }
 322     checkmclim(as);
 323   }
 324 }
 325 
 326 /* Setup result reg/sp for call. Evict scratch regs. */
 327 static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
 328 {
 329   RegSet drop = RSET_SCRATCH;
 330 #if LJ_32
 331   int hiop = ((ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t));
 332 #endif
 333 #if !LJ_SOFTFP
 334   if ((ci->flags & CCI_NOFPRCLOBBER))
 335     drop &= ~RSET_FPR;
 336 #endif
 337   if (ra_hasreg(ir->r))
 338     rset_clear(drop, ir->r);  /* Dest reg handled below. */
 339 #if LJ_32
 340   if (hiop && ra_hasreg((ir+1)->r))
 341     rset_clear(drop, (ir+1)->r);  /* Dest reg handled below. */
 342 #endif
 343   ra_evictset(as, drop);  /* Evictions must be performed first. */
 344   if (ra_used(ir)) {
 345     lua_assert(!irt_ispri(ir->t));
 346     if (!LJ_SOFTFP && irt_isfp(ir->t)) {
 347       if ((ci->flags & CCI_CASTU64)) {
 348         int32_t ofs = sps_scale(ir->s);
 349         Reg dest = ir->r;
 350         if (ra_hasreg(dest)) {
 351           ra_free(as, dest);
 352           ra_modified(as, dest);
 353 #if LJ_32
 354           emit_tg(as, MIPSI_MTC1, RID_RETHI, dest+1);
 355           emit_tg(as, MIPSI_MTC1, RID_RETLO, dest);
 356 #else
 357           emit_tg(as, MIPSI_DMTC1, RID_RET, dest);
 358 #endif
 359         }
 360         if (ofs) {
 361 #if LJ_32
 362           emit_tsi(as, MIPSI_SW, RID_RETLO, RID_SP, ofs+(LJ_BE?4:0));
 363           emit_tsi(as, MIPSI_SW, RID_RETHI, RID_SP, ofs+(LJ_BE?0:4));
 364 #else
 365           emit_tsi(as, MIPSI_SD, RID_RET, RID_SP, ofs);
 366 #endif
 367         }
 368       } else {
 369         ra_destreg(as, ir, RID_FPRET);
 370       }
 371 #if LJ_32
 372     } else if (hiop) {
 373       ra_destpair(as, ir);
 374 #endif
 375     } else {
 376       ra_destreg(as, ir, RID_RET);
 377     }
 378   }
 379 }
 380 
 381 static void asm_callx(ASMState *as, IRIns *ir)
 382 {
 383   IRRef args[CCI_NARGS_MAX*2];
 384   CCallInfo ci;
 385   IRRef func;
 386   IRIns *irf;
 387   ci.flags = asm_callx_flags(as, ir);
 388   asm_collectargs(as, ir, &ci, args);
 389   asm_setupresult(as, ir, &ci);
 390   func = ir->op2; irf = IR(func);
 391   if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
 392   if (irref_isk(func)) {  /* Call to constant address. */
 393     ci.func = (ASMFunction)(void *)get_kval(irf);
 394   } else {  /* Need specific register for indirect calls. */
 395     Reg r = ra_alloc1(as, func, RID2RSET(RID_CFUNCADDR));
 396     MCode *p = as->mcp;
 397     if (r == RID_CFUNCADDR)
 398       *--p = MIPSI_NOP;
 399     else
 400       *--p = MIPSI_MOVE | MIPSF_D(RID_CFUNCADDR) | MIPSF_S(r);
 401     *--p = MIPSI_JALR | MIPSF_S(r);
 402     as->mcp = p;
 403     ci.func = (ASMFunction)(void *)0;
 404   }
 405   asm_gencall(as, &ci, args);
 406 }
 407 
 408 #if !LJ_SOFTFP
 409 static void asm_callround(ASMState *as, IRIns *ir, IRCallID id)
 410 {
 411   /* The modified regs must match with the *.dasc implementation. */
 412   RegSet drop = RID2RSET(RID_R1)|RID2RSET(RID_R12)|RID2RSET(RID_FPRET)|
 413                 RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(REGARG_FIRSTFPR);
 414   if (ra_hasreg(ir->r)) rset_clear(drop, ir->r);
 415   ra_evictset(as, drop);
 416   ra_destreg(as, ir, RID_FPRET);
 417   emit_call(as, (void *)lj_ir_callinfo[id].func, 0);
 418   ra_leftov(as, REGARG_FIRSTFPR, ir->op1);
 419 }
 420 #endif
 421 
 422 /* -- Returns ------------------------------------------------------------- */
 423 
 424 /* Return to lower frame. Guard that it goes to the right spot. */
 425 static void asm_retf(ASMState *as, IRIns *ir)
 426 {
 427   Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
 428   void *pc = ir_kptr(IR(ir->op2));
 429   int32_t delta = 1+LJ_FR2+bc_a(*((const BCIns *)pc - 1));
 430   as->topslot -= (BCReg)delta;
 431   if ((int32_t)as->topslot < 0) as->topslot = 0;
 432   irt_setmark(IR(REF_BASE)->t);  /* Children must not coalesce with BASE reg. */
 433   emit_setgl(as, base, jit_base);
 434   emit_addptr(as, base, -8*delta);
 435   asm_guard(as, MIPSI_BNE, RID_TMP,
 436             ra_allock(as, igcptr(pc), rset_exclude(RSET_GPR, base)));
 437   emit_tsi(as, MIPSI_AL, RID_TMP, base, -8);
 438 }
 439 
 440 /* -- Type conversions ---------------------------------------------------- */
 441 
 442 #if !LJ_SOFTFP
 443 static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
 444 {
 445   Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
 446   Reg dest = ra_dest(as, ir, RSET_GPR);
 447   asm_guard(as, MIPSI_BC1F, 0, 0);
 448   emit_fgh(as, MIPSI_C_EQ_D, 0, tmp, left);
 449   emit_fg(as, MIPSI_CVT_D_W, tmp, tmp);
 450   emit_tg(as, MIPSI_MFC1, dest, tmp);
 451   emit_fg(as, MIPSI_CVT_W_D, tmp, left);
 452 }
 453 
 454 static void asm_tobit(ASMState *as, IRIns *ir)
 455 {
 456   RegSet allow = RSET_FPR;
 457   Reg dest = ra_dest(as, ir, RSET_GPR);
 458   Reg left = ra_alloc1(as, ir->op1, allow);
 459   Reg right = ra_alloc1(as, ir->op2, rset_clear(allow, left));
 460   Reg tmp = ra_scratch(as, rset_clear(allow, right));
 461   emit_tg(as, MIPSI_MFC1, dest, tmp);
 462   emit_fgh(as, MIPSI_ADD_D, tmp, left, right);
 463 }
 464 #elif LJ_64  /* && LJ_SOFTFP */
 465 static void asm_tointg(ASMState *as, IRIns *ir, Reg r)
 466 {
 467   /* The modified regs must match with the *.dasc implementation. */
 468   RegSet drop = RID2RSET(REGARG_FIRSTGPR)|RID2RSET(RID_RET)|RID2RSET(RID_RET+1)|
 469                 RID2RSET(RID_R1)|RID2RSET(RID_R12);
 470   if (ra_hasreg(ir->r)) rset_clear(drop, ir->r);
 471   ra_evictset(as, drop);
 472   /* Return values are in RID_RET (converted value) and RID_RET+1 (status). */
 473   ra_destreg(as, ir, RID_RET);
 474   asm_guard(as, MIPSI_BNE, RID_RET+1, RID_ZERO);
 475   emit_call(as, (void *)lj_ir_callinfo[IRCALL_lj_vm_tointg].func, 0);
 476   if (r == RID_NONE)
 477     ra_leftov(as, REGARG_FIRSTGPR, ir->op1);
 478   else if (r != REGARG_FIRSTGPR)
 479     emit_move(as, REGARG_FIRSTGPR, r);
 480 }
 481 
 482 static void asm_tobit(ASMState *as, IRIns *ir)
 483 {
 484   Reg dest = ra_dest(as, ir, RSET_GPR);
 485   emit_dta(as, MIPSI_SLL, dest, dest, 0);
 486   asm_callid(as, ir, IRCALL_lj_vm_tobit);
 487 }
 488 #endif
 489 
 490 static void asm_conv(ASMState *as, IRIns *ir)
 491 {
 492   IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
 493 #if !LJ_SOFTFP32
 494   int stfp = (st == IRT_NUM || st == IRT_FLOAT);
 495 #endif
 496 #if LJ_64
 497   int st64 = (st == IRT_I64 || st == IRT_U64 || st == IRT_P64);
 498 #endif
 499   IRRef lref = ir->op1;
 500 #if LJ_32
 501   lua_assert(!(irt_isint64(ir->t) ||
 502                (st == IRT_I64 || st == IRT_U64))); /* Handled by SPLIT. */
 503 #endif
 504 #if LJ_SOFTFP32
 505   /* FP conversions are handled by SPLIT. */
 506   lua_assert(!irt_isfp(ir->t) && !(st == IRT_NUM || st == IRT_FLOAT));
 507   /* Can't check for same types: SPLIT uses CONV int.int + BXOR for sfp NEG. */
 508 #else
 509   lua_assert(irt_type(ir->t) != st);
 510 #if !LJ_SOFTFP
 511   if (irt_isfp(ir->t)) {
 512     Reg dest = ra_dest(as, ir, RSET_FPR);
 513     if (stfp) {  /* FP to FP conversion. */
 514       emit_fg(as, st == IRT_NUM ? MIPSI_CVT_S_D : MIPSI_CVT_D_S,
 515               dest, ra_alloc1(as, lref, RSET_FPR));
 516     } else if (st == IRT_U32) {  /* U32 to FP conversion. */
 517       /* y = (x ^ 0x8000000) + 2147483648.0 */
 518       Reg left = ra_alloc1(as, lref, RSET_GPR);
 519       Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, dest));
 520       if (irt_isfloat(ir->t))
 521         emit_fg(as, MIPSI_CVT_S_D, dest, dest);
 522       /* Must perform arithmetic with doubles to keep the precision. */
 523       emit_fgh(as, MIPSI_ADD_D, dest, dest, tmp);
 524       emit_fg(as, MIPSI_CVT_D_W, dest, dest);
 525       emit_lsptr(as, MIPSI_LDC1, (tmp & 31),
 526                  (void *)&as->J->k64[LJ_K64_2P31], RSET_GPR);
 527       emit_tg(as, MIPSI_MTC1, RID_TMP, dest);
 528       emit_dst(as, MIPSI_XOR, RID_TMP, RID_TMP, left);
 529       emit_ti(as, MIPSI_LUI, RID_TMP, 0x8000);
 530 #if LJ_64
 531     } else if(st == IRT_U64) {  /* U64 to FP conversion. */
 532       /* if (x >= 1u<<63) y = (double)(int64_t)(x&(1u<<63)-1) + pow(2.0, 63) */
 533       Reg left = ra_alloc1(as, lref, RSET_GPR);
 534       Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, dest));
 535       MCLabel l_end = emit_label(as);
 536       if (irt_isfloat(ir->t)) {
 537         emit_fgh(as, MIPSI_ADD_S, dest, dest, tmp);
 538         emit_lsptr(as, MIPSI_LWC1, (tmp & 31), (void *)&as->J->k32[LJ_K32_2P63],
 539                    rset_exclude(RSET_GPR, left));
 540         emit_fg(as, MIPSI_CVT_S_L, dest, dest);
 541       } else {
 542         emit_fgh(as, MIPSI_ADD_D, dest, dest, tmp);
 543         emit_lsptr(as, MIPSI_LDC1, (tmp & 31), (void *)&as->J->k64[LJ_K64_2P63],
 544                    rset_exclude(RSET_GPR, left));
 545         emit_fg(as, MIPSI_CVT_D_L, dest, dest);
 546       }
 547       emit_branch(as, MIPSI_BGEZ, left, RID_ZERO, l_end);
 548       emit_tg(as, MIPSI_DMTC1, RID_TMP, dest);
 549       emit_tsml(as, MIPSI_DEXTM, RID_TMP, left, 30, 0);
 550 #endif
 551     } else {  /* Integer to FP conversion. */
 552       Reg left = ra_alloc1(as, lref, RSET_GPR);
 553 #if LJ_32
 554       emit_fg(as, irt_isfloat(ir->t) ? MIPSI_CVT_S_W : MIPSI_CVT_D_W,
 555               dest, dest);
 556       emit_tg(as, MIPSI_MTC1, left, dest);
 557 #else
 558       MIPSIns mi = irt_isfloat(ir->t) ?
 559         (st64 ? MIPSI_CVT_S_L : MIPSI_CVT_S_W) :
 560         (st64 ? MIPSI_CVT_D_L : MIPSI_CVT_D_W);
 561       emit_fg(as, mi, dest, dest);
 562       emit_tg(as, st64 ? MIPSI_DMTC1 : MIPSI_MTC1, left, dest);
 563 #endif
 564     }
 565   } else if (stfp) {  /* FP to integer conversion. */
 566     if (irt_isguard(ir->t)) {
 567       /* Checked conversions are only supported from number to int. */
 568       lua_assert(irt_isint(ir->t) && st == IRT_NUM);
 569       asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
 570     } else {
 571       Reg dest = ra_dest(as, ir, RSET_GPR);
 572       Reg left = ra_alloc1(as, lref, RSET_FPR);
 573       Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
 574       if (irt_isu32(ir->t)) {  /* FP to U32 conversion. */
 575         /* y = (int)floor(x - 2147483648.0) ^ 0x80000000 */
 576         emit_dst(as, MIPSI_XOR, dest, dest, RID_TMP);
 577         emit_ti(as, MIPSI_LUI, RID_TMP, 0x8000);
 578         emit_tg(as, MIPSI_MFC1, dest, tmp);
 579         emit_fg(as, st == IRT_FLOAT ? MIPSI_FLOOR_W_S : MIPSI_FLOOR_W_D,
 580                 tmp, tmp);
 581         emit_fgh(as, st == IRT_FLOAT ? MIPSI_SUB_S : MIPSI_SUB_D,
 582                  tmp, left, tmp);
 583         if (st == IRT_FLOAT)
 584           emit_lsptr(as, MIPSI_LWC1, (tmp & 31),
 585                      (void *)&as->J->k32[LJ_K32_2P31], RSET_GPR);
 586         else
 587           emit_lsptr(as, MIPSI_LDC1, (tmp & 31),
 588                      (void *)&as->J->k64[LJ_K64_2P31], RSET_GPR);
 589 #if LJ_64
 590       } else if (irt_isu64(ir->t)) {  /* FP to U64 conversion. */
 591         MCLabel l_end;
 592         emit_tg(as, MIPSI_DMFC1, dest, tmp);
 593         l_end = emit_label(as);
 594         /* For inputs >= 2^63 add -2^64 and convert again. */
 595         if (st == IRT_NUM) {
 596           emit_fg(as, MIPSI_TRUNC_L_D, tmp, tmp);
 597           emit_fgh(as, MIPSI_ADD_D, tmp, left, tmp);
 598           emit_lsptr(as, MIPSI_LDC1, (tmp & 31),
 599                      (void *)&as->J->k64[LJ_K64_M2P64],
 600                      rset_exclude(RSET_GPR, dest));
 601           emit_fg(as, MIPSI_TRUNC_L_D, tmp, left);  /* Delay slot. */
 602           emit_branch(as, MIPSI_BC1T, 0, 0, l_end);
 603           emit_fgh(as, MIPSI_C_OLT_D, 0, left, tmp);
 604           emit_lsptr(as, MIPSI_LDC1, (tmp & 31),
 605                      (void *)&as->J->k64[LJ_K64_2P63],
 606                      rset_exclude(RSET_GPR, dest));
 607         } else {
 608           emit_fg(as, MIPSI_TRUNC_L_S, tmp, tmp);
 609           emit_fgh(as, MIPSI_ADD_S, tmp, left, tmp);
 610           emit_lsptr(as, MIPSI_LWC1, (tmp & 31),
 611                      (void *)&as->J->k32[LJ_K32_M2P64],
 612                      rset_exclude(RSET_GPR, dest));
 613           emit_fg(as, MIPSI_TRUNC_L_S, tmp, left);  /* Delay slot. */
 614           emit_branch(as, MIPSI_BC1T, 0, 0, l_end);
 615           emit_fgh(as, MIPSI_C_OLT_S, 0, left, tmp);
 616           emit_lsptr(as, MIPSI_LWC1, (tmp & 31),
 617                      (void *)&as->J->k32[LJ_K32_2P63],
 618                      rset_exclude(RSET_GPR, dest));
 619         }
 620 #endif
 621       } else {
 622 #if LJ_32
 623         emit_tg(as, MIPSI_MFC1, dest, tmp);
 624         emit_fg(as, st == IRT_FLOAT ? MIPSI_TRUNC_W_S : MIPSI_TRUNC_W_D,
 625                 tmp, left);
 626 #else
 627         MIPSIns mi = irt_is64(ir->t) ?
 628           (st == IRT_NUM ? MIPSI_TRUNC_L_D : MIPSI_TRUNC_L_S) :
 629           (st == IRT_NUM ? MIPSI_TRUNC_W_D : MIPSI_TRUNC_W_S);
 630         emit_tg(as, irt_is64(ir->t) ? MIPSI_DMFC1 : MIPSI_MFC1, dest, left);
 631         emit_fg(as, mi, left, left);
 632 #endif
 633       }
 634     }
 635   } else
 636 #else
 637   if (irt_isfp(ir->t)) {
 638 #if LJ_64 && LJ_HASFFI
 639     if (stfp) {  /* FP to FP conversion. */
 640       asm_callid(as, ir, irt_isnum(ir->t) ? IRCALL_softfp_f2d :
 641                                             IRCALL_softfp_d2f);
 642     } else {  /* Integer to FP conversion. */
 643       IRCallID cid = ((IRT_IS64 >> st) & 1) ?
 644         (irt_isnum(ir->t) ?
 645          (st == IRT_I64 ? IRCALL_fp64_l2d : IRCALL_fp64_ul2d) :
 646          (st == IRT_I64 ? IRCALL_fp64_l2f : IRCALL_fp64_ul2f)) :
 647         (irt_isnum(ir->t) ?
 648          (st == IRT_INT ? IRCALL_softfp_i2d : IRCALL_softfp_ui2d) :
 649          (st == IRT_INT ? IRCALL_softfp_i2f : IRCALL_softfp_ui2f));
 650       asm_callid(as, ir, cid);
 651     }
 652 #else
 653     asm_callid(as, ir, IRCALL_softfp_i2d);
 654 #endif
 655   } else if (stfp) {  /* FP to integer conversion. */
 656     if (irt_isguard(ir->t)) {
 657       /* Checked conversions are only supported from number to int. */
 658       lua_assert(irt_isint(ir->t) && st == IRT_NUM);
 659       asm_tointg(as, ir, RID_NONE);
 660     } else {
 661       IRCallID cid = irt_is64(ir->t) ?
 662         ((st == IRT_NUM) ?
 663          (irt_isi64(ir->t) ? IRCALL_fp64_d2l : IRCALL_fp64_d2ul) :
 664          (irt_isi64(ir->t) ? IRCALL_fp64_f2l : IRCALL_fp64_f2ul)) :
 665         ((st == IRT_NUM) ?
 666          (irt_isint(ir->t) ? IRCALL_softfp_d2i : IRCALL_softfp_d2ui) :
 667          (irt_isint(ir->t) ? IRCALL_softfp_f2i : IRCALL_softfp_f2ui));
 668       asm_callid(as, ir, cid);
 669     }
 670   } else
 671 #endif
 672 #endif
 673   {
 674     Reg dest = ra_dest(as, ir, RSET_GPR);
 675     if (st >= IRT_I8 && st <= IRT_U16) {  /* Extend to 32 bit integer. */
 676       Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
 677       lua_assert(irt_isint(ir->t) || irt_isu32(ir->t));
 678       if ((ir->op2 & IRCONV_SEXT)) {
 679         if (LJ_64 || (as->flags & JIT_F_MIPSXXR2)) {
 680           emit_dst(as, st == IRT_I8 ? MIPSI_SEB : MIPSI_SEH, dest, 0, left);
 681         } else {
 682           uint32_t shift = st == IRT_I8 ? 24 : 16;
 683           emit_dta(as, MIPSI_SRA, dest, dest, shift);
 684           emit_dta(as, MIPSI_SLL, dest, left, shift);
 685         }
 686       } else {
 687         emit_tsi(as, MIPSI_ANDI, dest, left,
 688                  (int32_t)(st == IRT_U8 ? 0xff : 0xffff));
 689       }
 690     } else {  /* 32/64 bit integer conversions. */
 691 #if LJ_32
 692       /* Only need to handle 32/32 bit no-op (cast) on 32 bit archs. */
 693       ra_leftov(as, dest, lref);  /* Do nothing, but may need to move regs. */
 694 #else
 695       if (irt_is64(ir->t)) {
 696         if (st64) {
 697           /* 64/64 bit no-op (cast)*/
 698           ra_leftov(as, dest, lref);
 699         } else {
 700           Reg left = ra_alloc1(as, lref, RSET_GPR);
 701           if ((ir->op2 & IRCONV_SEXT)) {  /* 32 to 64 bit sign extension. */
 702             emit_dta(as, MIPSI_SLL, dest, left, 0);
 703           } else {  /* 32 to 64 bit zero extension. */
 704             emit_tsml(as, MIPSI_DEXT, dest, left, 31, 0);
 705           }
 706         }
 707       } else {
 708         if (st64) {
 709           /* This is either a 32 bit reg/reg mov which zeroes the hiword
 710           ** or a load of the loword from a 64 bit address.
 711           */
 712           Reg left = ra_alloc1(as, lref, RSET_GPR);
 713           emit_tsml(as, MIPSI_DEXT, dest, left, 31, 0);
 714         } else {  /* 32/32 bit no-op (cast). */
 715           /* Do nothing, but may need to move regs. */
 716           ra_leftov(as, dest, lref);
 717         }
 718       }
 719 #endif
 720     }
 721   }
 722 }
 723 
 724 static void asm_strto(ASMState *as, IRIns *ir)
 725 {
 726   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
 727   IRRef args[2];
 728   int32_t ofs = 0;
 729 #if LJ_SOFTFP32
 730   ra_evictset(as, RSET_SCRATCH);
 731   if (ra_used(ir)) {
 732     if (ra_hasspill(ir->s) && ra_hasspill((ir+1)->s) &&
 733         (ir->s & 1) == LJ_BE && (ir->s ^ 1) == (ir+1)->s) {
 734       int i;
 735       for (i = 0; i < 2; i++) {
 736         Reg r = (ir+i)->r;
 737         if (ra_hasreg(r)) {
 738           ra_free(as, r);
 739           ra_modified(as, r);
 740           emit_spload(as, ir+i, r, sps_scale((ir+i)->s));
 741         }
 742       }
 743       ofs = sps_scale(ir->s & ~1);
 744     } else {
 745       Reg rhi = ra_dest(as, ir+1, RSET_GPR);
 746       Reg rlo = ra_dest(as, ir, rset_exclude(RSET_GPR, rhi));
 747       emit_tsi(as, MIPSI_LW, rhi, RID_SP, ofs+(LJ_BE?0:4));
 748       emit_tsi(as, MIPSI_LW, rlo, RID_SP, ofs+(LJ_BE?4:0));
 749     }
 750   }
 751 #else
 752   RegSet drop = RSET_SCRATCH;
 753   if (ra_hasreg(ir->r)) rset_set(drop, ir->r);  /* Spill dest reg (if any). */
 754   ra_evictset(as, drop);
 755   ofs = sps_scale(ir->s);
 756 #endif
 757   asm_guard(as, MIPSI_BEQ, RID_RET, RID_ZERO);  /* Test return status. */
 758   args[0] = ir->op1;      /* GCstr *str */
 759   args[1] = ASMREF_TMP1;  /* TValue *n  */
 760   asm_gencall(as, ci, args);
 761   /* Store the result to the spill slot or temp slots. */
 762   emit_tsi(as, MIPSI_AADDIU, ra_releasetmp(as, ASMREF_TMP1),
 763            RID_SP, ofs);
 764 }
 765 
 766 /* -- Memory references --------------------------------------------------- */
 767 
 768 #if LJ_64
 769 /* Store tagged value for ref at base+ofs. */
 770 static void asm_tvstore64(ASMState *as, Reg base, int32_t ofs, IRRef ref)
 771 {
 772   RegSet allow = rset_exclude(RSET_GPR, base);
 773   IRIns *ir = IR(ref);
 774   lua_assert(irt_ispri(ir->t) || irt_isaddr(ir->t) || irt_isinteger(ir->t));
 775   if (irref_isk(ref)) {
 776     TValue k;
 777     lj_ir_kvalue(as->J->L, &k, ir);
 778     emit_tsi(as, MIPSI_SD, ra_allock(as, (int64_t)k.u64, allow), base, ofs);
 779   } else {
 780     Reg src = ra_alloc1(as, ref, allow);
 781     Reg type = ra_allock(as, (int64_t)irt_toitype(ir->t) << 47,
 782                          rset_exclude(allow, src));
 783     emit_tsi(as, MIPSI_SD, RID_TMP, base, ofs);
 784     if (irt_isinteger(ir->t)) {
 785       emit_dst(as, MIPSI_DADDU, RID_TMP, RID_TMP, type);
 786       emit_tsml(as, MIPSI_DEXT, RID_TMP, src, 31, 0);
 787     } else {
 788       emit_dst(as, MIPSI_DADDU, RID_TMP, src, type);
 789     }
 790   }
 791 }
 792 #endif
 793 
 794 /* Get pointer to TValue. */
 795 static void asm_tvptr(ASMState *as, Reg dest, IRRef ref)
 796 {
 797   IRIns *ir = IR(ref);
 798   if (irt_isnum(ir->t)) {
 799     if (irref_isk(ref))  /* Use the number constant itself as a TValue. */
 800       ra_allockreg(as, igcptr(ir_knum(ir)), dest);
 801     else  /* Otherwise force a spill and use the spill slot. */
 802       emit_tsi(as, MIPSI_AADDIU, dest, RID_SP, ra_spill(as, ir));
 803   } else {
 804     /* Otherwise use g->tmptv to hold the TValue. */
 805 #if LJ_32
 806     RegSet allow = rset_exclude(RSET_GPR, dest);
 807     Reg type;
 808     emit_tsi(as, MIPSI_ADDIU, dest, RID_JGL, (int32_t)(offsetof(global_State, tmptv)-32768));
 809     if (!irt_ispri(ir->t)) {
 810       Reg src = ra_alloc1(as, ref, allow);
 811       emit_setgl(as, src, tmptv.gcr);
 812     }
 813     if (LJ_SOFTFP && (ir+1)->o == IR_HIOP)
 814       type = ra_alloc1(as, ref+1, allow);
 815     else
 816       type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
 817     emit_setgl(as, type, tmptv.it);
 818 #else
 819     asm_tvstore64(as, dest, 0, ref);
 820     emit_tsi(as, MIPSI_DADDIU, dest, RID_JGL,
 821              (int32_t)(offsetof(global_State, tmptv)-32768));
 822 #endif
 823   }
 824 }
 825 
 826 static void asm_aref(ASMState *as, IRIns *ir)
 827 {
 828   Reg dest = ra_dest(as, ir, RSET_GPR);
 829   Reg idx, base;
 830   if (irref_isk(ir->op2)) {
 831     IRRef tab = IR(ir->op1)->op1;
 832     int32_t ofs = asm_fuseabase(as, tab);
 833     IRRef refa = ofs ? tab : ir->op1;
 834     ofs += 8*IR(ir->op2)->i;
 835     if (checki16(ofs)) {
 836       base = ra_alloc1(as, refa, RSET_GPR);
 837       emit_tsi(as, MIPSI_AADDIU, dest, base, ofs);
 838       return;
 839     }
 840   }
 841   base = ra_alloc1(as, ir->op1, RSET_GPR);
 842   idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
 843   emit_dst(as, MIPSI_AADDU, dest, RID_TMP, base);
 844   emit_dta(as, MIPSI_SLL, RID_TMP, idx, 3);
 845 }
 846 
 847 /* Inlined hash lookup. Specialized for key type and for const keys.
 848 ** The equivalent C code is:
 849 **   Node *n = hashkey(t, key);
 850 **   do {
 851 **     if (lj_obj_equal(&n->key, key)) return &n->val;
 852 **   } while ((n = nextnode(n)));
 853 **   return niltv(L);
 854 */
 855 static void asm_href(ASMState *as, IRIns *ir, IROp merge)
 856 {
 857   RegSet allow = RSET_GPR;
 858   int destused = ra_used(ir);
 859   Reg dest = ra_dest(as, ir, allow);
 860   Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
 861   Reg key = RID_NONE, type = RID_NONE, tmpnum = RID_NONE, tmp1 = RID_TMP, tmp2;
 862 #if LJ_64
 863   Reg cmp64 = RID_NONE;
 864 #endif
 865   IRRef refkey = ir->op2;
 866   IRIns *irkey = IR(refkey);
 867   int isk = irref_isk(refkey);
 868   IRType1 kt = irkey->t;
 869   uint32_t khash;
 870   MCLabel l_end, l_loop, l_next;
 871 
 872   rset_clear(allow, tab);
 873 #if LJ_SOFTFP32
 874   if (!isk) {
 875     key = ra_alloc1(as, refkey, allow);
 876     rset_clear(allow, key);
 877     if (irkey[1].o == IR_HIOP) {
 878       if (ra_hasreg((irkey+1)->r)) {
 879         type = tmpnum = (irkey+1)->r;
 880         tmp1 = ra_scratch(as, allow);
 881         rset_clear(allow, tmp1);
 882         ra_noweak(as, tmpnum);
 883       } else {
 884         type = tmpnum = ra_allocref(as, refkey+1, allow);
 885       }
 886       rset_clear(allow, tmpnum);
 887     } else {
 888       type = ra_allock(as, (int32_t)irt_toitype(irkey->t), allow);
 889       rset_clear(allow, type);
 890     }
 891   }
 892 #else
 893   if (!LJ_SOFTFP && irt_isnum(kt)) {
 894     key = ra_alloc1(as, refkey, RSET_FPR);
 895     tmpnum = ra_scratch(as, rset_exclude(RSET_FPR, key));
 896   } else if (!irt_ispri(kt)) {
 897     key = ra_alloc1(as, refkey, allow);
 898     rset_clear(allow, key);
 899 #if LJ_32
 900     type = ra_allock(as, (int32_t)irt_toitype(irkey->t), allow);
 901     rset_clear(allow, type);
 902 #endif
 903   }
 904 #endif
 905   tmp2 = ra_scratch(as, allow);
 906   rset_clear(allow, tmp2);
 907 #if LJ_64
 908   if (LJ_SOFTFP || !irt_isnum(kt)) {
 909     /* Allocate cmp64 register used for 64-bit comparisons */
 910     if (LJ_SOFTFP && irt_isnum(kt)) {
 911       cmp64 = key;
 912     } else if (!isk && irt_isaddr(kt)) {
 913       cmp64 = tmp2;
 914     } else {
 915       int64_t k;
 916       if (isk && irt_isaddr(kt)) {
 917         k = ((int64_t)irt_toitype(irkey->t) << 47) | irkey[1].tv.u64;
 918       } else {
 919         lua_assert(irt_ispri(kt) && !irt_isnil(kt));
 920         k = ~((int64_t)~irt_toitype(ir->t) << 47);
 921       }
 922       cmp64 = ra_allock(as, k, allow);
 923       rset_clear(allow, cmp64);
 924     }
 925   }
 926 #endif
 927 
 928   /* Key not found in chain: jump to exit (if merged) or load niltv. */
 929   l_end = emit_label(as);
 930   as->invmcp = NULL;
 931   if (merge == IR_NE)
 932     asm_guard(as, MIPSI_B, RID_ZERO, RID_ZERO);
 933   else if (destused)
 934     emit_loada(as, dest, niltvg(J2G(as->J)));
 935   /* Follow hash chain until the end. */
 936   emit_move(as, dest, tmp1);
 937   l_loop = --as->mcp;
 938   emit_tsi(as, MIPSI_AL, tmp1, dest, (int32_t)offsetof(Node, next));
 939   l_next = emit_label(as);
 940 
 941   /* Type and value comparison. */
 942   if (merge == IR_EQ) {  /* Must match asm_guard(). */
 943     emit_ti(as, MIPSI_LI, RID_TMP, as->snapno);
 944     l_end = asm_exitstub_addr(as);
 945   }
 946   if (!LJ_SOFTFP && irt_isnum(kt)) {
 947     emit_branch(as, MIPSI_BC1T, 0, 0, l_end);
 948     emit_fgh(as, MIPSI_C_EQ_D, 0, tmpnum, key);
 949     *--as->mcp = MIPSI_NOP;  /* Avoid NaN comparison overhead. */
 950     emit_branch(as, MIPSI_BEQ, tmp1, RID_ZERO, l_next);
 951     emit_tsi(as, MIPSI_SLTIU, tmp1, tmp1, (int32_t)LJ_TISNUM);
 952 #if LJ_32
 953     emit_hsi(as, MIPSI_LDC1, tmpnum, dest, (int32_t)offsetof(Node, key.n));
 954   } else {
 955     if (irt_ispri(kt)) {
 956       emit_branch(as, MIPSI_BEQ, tmp1, type, l_end);
 957     } else {
 958       emit_branch(as, MIPSI_BEQ, tmp2, key, l_end);
 959       emit_tsi(as, MIPSI_LW, tmp2, dest, (int32_t)offsetof(Node, key.gcr));
 960       emit_branch(as, MIPSI_BNE, tmp1, type, l_next);
 961     }
 962   }
 963   emit_tsi(as, MIPSI_LW, tmp1, dest, (int32_t)offsetof(Node, key.it));
 964   *l_loop = MIPSI_BNE | MIPSF_S(tmp1) | ((as->mcp-l_loop-1) & 0xffffu);
 965 #else
 966     emit_dta(as, MIPSI_DSRA32, tmp1, tmp1, 15);
 967     emit_tg(as, MIPSI_DMTC1, tmp1, tmpnum);
 968     emit_tsi(as, MIPSI_LD, tmp1, dest, (int32_t)offsetof(Node, key.u64));
 969   } else {
 970     emit_branch(as, MIPSI_BEQ, tmp1, cmp64, l_end);
 971     emit_tsi(as, MIPSI_LD, tmp1, dest, (int32_t)offsetof(Node, key.u64));
 972   }
 973   *l_loop = MIPSI_BNE | MIPSF_S(tmp1) | ((as->mcp-l_loop-1) & 0xffffu);
 974   if (!isk && irt_isaddr(kt)) {
 975     type = ra_allock(as, (int64_t)irt_toitype(kt) << 47, allow);
 976     emit_dst(as, MIPSI_DADDU, tmp2, key, type);
 977     rset_clear(allow, type);
 978   }
 979 #endif
 980 
 981   /* Load main position relative to tab->node into dest. */
 982   khash = isk ? ir_khash(irkey) : 1;
 983   if (khash == 0) {
 984     emit_tsi(as, MIPSI_AL, dest, tab, (int32_t)offsetof(GCtab, node));
 985   } else {
 986     Reg tmphash = tmp1;
 987     if (isk)
 988       tmphash = ra_allock(as, khash, allow);
 989     emit_dst(as, MIPSI_AADDU, dest, dest, tmp1);
 990     lua_assert(sizeof(Node) == 24);
 991     emit_dst(as, MIPSI_SUBU, tmp1, tmp2, tmp1);
 992     emit_dta(as, MIPSI_SLL, tmp1, tmp1, 3);
 993     emit_dta(as, MIPSI_SLL, tmp2, tmp1, 5);
 994     emit_dst(as, MIPSI_AND, tmp1, tmp2, tmphash);
 995     emit_tsi(as, MIPSI_AL, dest, tab, (int32_t)offsetof(GCtab, node));
 996     emit_tsi(as, MIPSI_LW, tmp2, tab, (int32_t)offsetof(GCtab, hmask));
 997     if (isk) {
 998       /* Nothing to do. */
 999     } else if (irt_isstr(kt)) {
1000       emit_tsi(as, MIPSI_LW, tmp1, key, (int32_t)offsetof(GCstr, hash));
1001     } else {  /* Must match with hash*() in lj_tab.c. */
1002       emit_dst(as, MIPSI_SUBU, tmp1, tmp1, tmp2);
1003       emit_rotr(as, tmp2, tmp2, dest, (-HASH_ROT3)&31);
1004       emit_dst(as, MIPSI_XOR, tmp1, tmp1, tmp2);
1005       emit_rotr(as, tmp1, tmp1, dest, (-HASH_ROT2-HASH_ROT1)&31);
1006       emit_dst(as, MIPSI_SUBU, tmp2, tmp2, dest);
1007 #if LJ_32
1008       if (LJ_SOFTFP ? (irkey[1].o == IR_HIOP) : irt_isnum(kt)) {
1009         emit_dst(as, MIPSI_XOR, tmp2, tmp2, tmp1);
1010         if ((as->flags & JIT_F_MIPSXXR2)) {
1011           emit_dta(as, MIPSI_ROTR, dest, tmp1, (-HASH_ROT1)&31);
1012         } else {
1013           emit_dst(as, MIPSI_OR, dest, dest, tmp1);
1014           emit_dta(as, MIPSI_SLL, tmp1, tmp1, HASH_ROT1);
1015           emit_dta(as, MIPSI_SRL, dest, tmp1, (-HASH_ROT1)&31);
1016         }
1017         emit_dst(as, MIPSI_ADDU, tmp1, tmp1, tmp1);
1018 #if LJ_SOFTFP
1019         emit_ds(as, MIPSI_MOVE, tmp1, type);
1020         emit_ds(as, MIPSI_MOVE, tmp2, key);
1021 #else
1022         emit_tg(as, MIPSI_MFC1, tmp2, key);
1023         emit_tg(as, MIPSI_MFC1, tmp1, key+1);
1024 #endif
1025       } else {
1026         emit_dst(as, MIPSI_XOR, tmp2, key, tmp1);
1027         emit_rotr(as, dest, tmp1, tmp2, (-HASH_ROT1)&31);
1028         emit_dst(as, MIPSI_ADDU, tmp1, key, ra_allock(as, HASH_BIAS, allow));
1029       }
1030 #else
1031       emit_dst(as, MIPSI_XOR, tmp2, tmp2, tmp1);
1032       emit_dta(as, MIPSI_ROTR, dest, tmp1, (-HASH_ROT1)&31);
1033       if (irt_isnum(kt)) {
1034         emit_dst(as, MIPSI_ADDU, tmp1, tmp1, tmp1);
1035         emit_dta(as, MIPSI_DSRA32, tmp1, LJ_SOFTFP ? key : tmp1, 0);
1036         emit_dta(as, MIPSI_SLL, tmp2, LJ_SOFTFP ? key : tmp1, 0);
1037 #if !LJ_SOFTFP
1038         emit_tg(as, MIPSI_DMFC1, tmp1, key);
1039 #endif
1040       } else {
1041         checkmclim(as);
1042         emit_dta(as, MIPSI_DSRA32, tmp1, tmp1, 0);
1043         emit_dta(as, MIPSI_SLL, tmp2, key, 0);
1044         emit_dst(as, MIPSI_DADDU, tmp1, key, type);
1045       }
1046 #endif
1047     }
1048   }
1049 }
1050 
1051 static void asm_hrefk(ASMState *as, IRIns *ir)
1052 {
1053   IRIns *kslot = IR(ir->op2);
1054   IRIns *irkey = IR(kslot->op1);
1055   int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
1056   int32_t kofs = ofs + (int32_t)offsetof(Node, key);
1057   Reg dest = (ra_used(ir)||ofs > 32736) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
1058   Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
1059   RegSet allow = rset_exclude(RSET_GPR, node);
1060   Reg idx = node;
1061 #if LJ_32
1062   Reg key = RID_NONE, type = RID_TMP;
1063   int32_t lo, hi;
1064 #else
1065   Reg key = ra_scratch(as, allow);
1066   int64_t k;
1067 #endif
1068   lua_assert(ofs % sizeof(Node) == 0);
1069   if (ofs > 32736) {
1070     idx = dest;
1071     rset_clear(allow, dest);
1072     kofs = (int32_t)offsetof(Node, key);
1073   } else if (ra_hasreg(dest)) {
1074     emit_tsi(as, MIPSI_AADDIU, dest, node, ofs);
1075   }
1076 #if LJ_32
1077   if (!irt_ispri(irkey->t)) {
1078     key = ra_scratch(as, allow);
1079     rset_clear(allow, key);
1080   }
1081   if (irt_isnum(irkey->t)) {
1082     lo = (int32_t)ir_knum(irkey)->u32.lo;
1083     hi = (int32_t)ir_knum(irkey)->u32.hi;
1084   } else {
1085     lo = irkey->i;
1086     hi = irt_toitype(irkey->t);
1087     if (!ra_hasreg(key))
1088       goto nolo;
1089   }
1090   asm_guard(as, MIPSI_BNE, key, lo ? ra_allock(as, lo, allow) : RID_ZERO);
1091 nolo:
1092   asm_guard(as, MIPSI_BNE, type, hi ? ra_allock(as, hi, allow) : RID_ZERO);
1093   if (ra_hasreg(key)) emit_tsi(as, MIPSI_LW, key, idx, kofs+(LJ_BE?4:0));
1094   emit_tsi(as, MIPSI_LW, type, idx, kofs+(LJ_BE?0:4));
1095 #else
1096   if (irt_ispri(irkey->t)) {
1097     lua_assert(!irt_isnil(irkey->t));
1098     k = ~((int64_t)~irt_toitype(irkey->t) << 47);
1099   } else if (irt_isnum(irkey->t)) {
1100     k = (int64_t)ir_knum(irkey)->u64;
1101   } else {
1102     k = ((int64_t)irt_toitype(irkey->t) << 47) | (int64_t)ir_kgc(irkey);
1103   }
1104   asm_guard(as, MIPSI_BNE, key, ra_allock(as, k, allow));
1105   emit_tsi(as, MIPSI_LD, key, idx, kofs);
1106 #endif
1107   if (ofs > 32736)
1108     emit_tsi(as, MIPSI_AADDU, dest, node, ra_allock(as, ofs, allow));
1109 }
1110 
1111 static void asm_uref(ASMState *as, IRIns *ir)
1112 {
1113   Reg dest = ra_dest(as, ir, RSET_GPR);
1114   if (irref_isk(ir->op1)) {
1115     GCfunc *fn = ir_kfunc(IR(ir->op1));
1116     MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
1117     emit_lsptr(as, MIPSI_AL, dest, v, RSET_GPR);
1118   } else {
1119     Reg uv = ra_scratch(as, RSET_GPR);
1120     Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
1121     if (ir->o == IR_UREFC) {
1122       asm_guard(as, MIPSI_BEQ, RID_TMP, RID_ZERO);
1123       emit_tsi(as, MIPSI_AADDIU, dest, uv, (int32_t)offsetof(GCupval, tv));
1124       emit_tsi(as, MIPSI_LBU, RID_TMP, uv, (int32_t)offsetof(GCupval, closed));
1125     } else {
1126       emit_tsi(as, MIPSI_AL, dest, uv, (int32_t)offsetof(GCupval, v));
1127     }
1128     emit_tsi(as, MIPSI_AL, uv, func, (int32_t)offsetof(GCfuncL, uvptr) +
1129              (int32_t)sizeof(MRef) * (int32_t)(ir->op2 >> 8));
1130   }
1131 }
1132 
1133 static void asm_fref(ASMState *as, IRIns *ir)
1134 {
1135   UNUSED(as); UNUSED(ir);
1136   lua_assert(!ra_used(ir));
1137 }
1138 
1139 static void asm_strref(ASMState *as, IRIns *ir)
1140 {
1141 #if LJ_32
1142   Reg dest = ra_dest(as, ir, RSET_GPR);
1143   IRRef ref = ir->op2, refk = ir->op1;
1144   int32_t ofs = (int32_t)sizeof(GCstr);
1145   Reg r;
1146   if (irref_isk(ref)) {
1147     IRRef tmp = refk; refk = ref; ref = tmp;
1148   } else if (!irref_isk(refk)) {
1149     Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
1150     IRIns *irr = IR(ir->op2);
1151     if (ra_hasreg(irr->r)) {
1152       ra_noweak(as, irr->r);
1153       right = irr->r;
1154     } else if (mayfuse(as, irr->op2) &&
1155                irr->o == IR_ADD && irref_isk(irr->op2) &&
1156                checki16(ofs + IR(irr->op2)->i)) {
1157       ofs += IR(irr->op2)->i;
1158       right = ra_alloc1(as, irr->op1, rset_exclude(RSET_GPR, left));
1159     } else {
1160       right = ra_allocref(as, ir->op2, rset_exclude(RSET_GPR, left));
1161     }
1162     emit_tsi(as, MIPSI_ADDIU, dest, dest, ofs);
1163     emit_dst(as, MIPSI_ADDU, dest, left, right);
1164     return;
1165   }
1166   r = ra_alloc1(as, ref, RSET_GPR);
1167   ofs += IR(refk)->i;
1168   if (checki16(ofs))
1169     emit_tsi(as, MIPSI_ADDIU, dest, r, ofs);
1170   else
1171     emit_dst(as, MIPSI_ADDU, dest, r,
1172              ra_allock(as, ofs, rset_exclude(RSET_GPR, r)));
1173 #else
1174   RegSet allow = RSET_GPR;
1175   Reg dest = ra_dest(as, ir, allow);
1176   Reg base = ra_alloc1(as, ir->op1, allow);
1177   IRIns *irr = IR(ir->op2);
1178   int32_t ofs = sizeof(GCstr);
1179   rset_clear(allow, base);
1180   if (irref_isk(ir->op2) && checki16(ofs + irr->i)) {
1181     emit_tsi(as, MIPSI_DADDIU, dest, base, ofs + irr->i);
1182   } else {
1183     emit_tsi(as, MIPSI_DADDIU, dest, dest, ofs);
1184     emit_dst(as, MIPSI_DADDU, dest, base, ra_alloc1(as, ir->op2, allow));
1185   }
1186 #endif
1187 }
1188 
1189 /* -- Loads and stores ---------------------------------------------------- */
1190 
1191 static MIPSIns asm_fxloadins(IRIns *ir)
1192 {
1193   switch (irt_type(ir->t)) {
1194   case IRT_I8: return MIPSI_LB;
1195   case IRT_U8: return MIPSI_LBU;
1196   case IRT_I16: return MIPSI_LH;
1197   case IRT_U16: return MIPSI_LHU;
1198   case IRT_NUM: lua_assert(!LJ_SOFTFP32); if (!LJ_SOFTFP) return MIPSI_LDC1;
1199   case IRT_FLOAT: if (!LJ_SOFTFP) return MIPSI_LWC1;
1200   default: return (LJ_64 && irt_is64(ir->t)) ? MIPSI_LD : MIPSI_LW;
1201   }
1202 }
1203 
1204 static MIPSIns asm_fxstoreins(IRIns *ir)
1205 {
1206   switch (irt_type(ir->t)) {
1207   case IRT_I8: case IRT_U8: return MIPSI_SB;
1208   case IRT_I16: case IRT_U16: return MIPSI_SH;
1209   case IRT_NUM: lua_assert(!LJ_SOFTFP32); if (!LJ_SOFTFP) return MIPSI_SDC1;
1210   case IRT_FLOAT: if (!LJ_SOFTFP) return MIPSI_SWC1;
1211   default: return (LJ_64 && irt_is64(ir->t)) ? MIPSI_SD : MIPSI_SW;
1212   }
1213 }
1214 
1215 static void asm_fload(ASMState *as, IRIns *ir)
1216 {
1217   Reg dest = ra_dest(as, ir, RSET_GPR);
1218   MIPSIns mi = asm_fxloadins(ir);
1219   Reg idx;
1220   int32_t ofs;
1221   if (ir->op1 == REF_NIL) {
1222     idx = RID_JGL;
1223     ofs = (ir->op2 << 2) - 32768 - GG_OFS(g);
1224   } else {
1225     idx = ra_alloc1(as, ir->op1, RSET_GPR);
1226     if (ir->op2 == IRFL_TAB_ARRAY) {
1227       ofs = asm_fuseabase(as, ir->op1);
1228       if (ofs) {  /* Turn the t->array load into an add for colocated arrays. */
1229         emit_tsi(as, MIPSI_AADDIU, dest, idx, ofs);
1230         return;
1231       }
1232     }
1233     ofs = field_ofs[ir->op2];
1234   }
1235   lua_assert(!irt_isfp(ir->t));
1236   emit_tsi(as, mi, dest, idx, ofs);
1237 }
1238 
1239 static void asm_fstore(ASMState *as, IRIns *ir)
1240 {
1241   if (ir->r != RID_SINK) {
1242     Reg src = ra_alloc1z(as, ir->op2, RSET_GPR);
1243     IRIns *irf = IR(ir->op1);
1244     Reg idx = ra_alloc1(as, irf->op1, rset_exclude(RSET_GPR, src));
1245     int32_t ofs = field_ofs[irf->op2];
1246     MIPSIns mi = asm_fxstoreins(ir);
1247     lua_assert(!irt_isfp(ir->t));
1248     emit_tsi(as, mi, src, idx, ofs);
1249   }
1250 }
1251 
1252 static void asm_xload(ASMState *as, IRIns *ir)
1253 {
1254   Reg dest = ra_dest(as, ir,
1255     (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
1256   lua_assert(!(ir->op2 & IRXLOAD_UNALIGNED));
1257   asm_fusexref(as, asm_fxloadins(ir), dest, ir->op1, RSET_GPR, 0);
1258 }
1259 
1260 static void asm_xstore_(ASMState *as, IRIns *ir, int32_t ofs)
1261 {
1262   if (ir->r != RID_SINK) {
1263     Reg src = ra_alloc1z(as, ir->op2,
1264       (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
1265     asm_fusexref(as, asm_fxstoreins(ir), src, ir->op1,
1266                  rset_exclude(RSET_GPR, src), ofs);
1267   }
1268 }
1269 
1270 #define asm_xstore(as, ir)      asm_xstore_(as, ir, 0)
1271 
1272 static void asm_ahuvload(ASMState *as, IRIns *ir)
1273 {
1274   int hiop = (LJ_SOFTFP32 && (ir+1)->o == IR_HIOP);
1275   Reg dest = RID_NONE, type = RID_TMP, idx;
1276   RegSet allow = RSET_GPR;
1277   int32_t ofs = 0;
1278   IRType1 t = ir->t;
1279   if (hiop) {
1280     t.irt = IRT_NUM;
1281     if (ra_used(ir+1)) {
1282       type = ra_dest(as, ir+1, allow);
1283       rset_clear(allow, type);
1284     }
1285   }
1286   if (ra_used(ir)) {
1287     lua_assert((LJ_SOFTFP32 ? 0 : irt_isnum(ir->t)) ||
1288                irt_isint(ir->t) || irt_isaddr(ir->t));
1289     dest = ra_dest(as, ir, (!LJ_SOFTFP && irt_isnum(t)) ? RSET_FPR : allow);
1290     rset_clear(allow, dest);
1291 #if LJ_64
1292     if (irt_isaddr(t))
1293       emit_tsml(as, MIPSI_DEXTM, dest, dest, 14, 0);
1294     else if (irt_isint(t))
1295       emit_dta(as, MIPSI_SLL, dest, dest, 0);
1296 #endif
1297   }
1298   idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
1299   rset_clear(allow, idx);
1300   if (irt_isnum(t)) {
1301     asm_guard(as, MIPSI_BEQ, RID_TMP, RID_ZERO);
1302     emit_tsi(as, MIPSI_SLTIU, RID_TMP, type, (int32_t)LJ_TISNUM);
1303   } else {
1304     asm_guard(as, MIPSI_BNE, type,
1305               ra_allock(as, (int32_t)irt_toitype(t), allow));
1306   }
1307 #if LJ_32
1308   if (ra_hasreg(dest)) {
1309     if (!LJ_SOFTFP && irt_isnum(t))
1310       emit_hsi(as, MIPSI_LDC1, dest, idx, ofs);
1311     else
1312       emit_tsi(as, MIPSI_LW, dest, idx, ofs+(LJ_BE?4:0));
1313   }
1314   emit_tsi(as, MIPSI_LW, type, idx, ofs+(LJ_BE?0:4));
1315 #else
1316   if (ra_hasreg(dest)) {
1317     if (!LJ_SOFTFP && irt_isnum(t)) {
1318       emit_hsi(as, MIPSI_LDC1, dest, idx, ofs);
1319       dest = type;
1320     }
1321   } else {
1322     dest = type;
1323   }
1324   emit_dta(as, MIPSI_DSRA32, type, dest, 15);
1325   emit_tsi(as, MIPSI_LD, dest, idx, ofs);
1326 #endif
1327 }
1328 
1329 static void asm_ahustore(ASMState *as, IRIns *ir)
1330 {
1331   RegSet allow = RSET_GPR;
1332   Reg idx, src = RID_NONE, type = RID_NONE;
1333   int32_t ofs = 0;
1334   if (ir->r == RID_SINK)
1335     return;
1336   if (!LJ_SOFTFP32 && irt_isnum(ir->t)) {
1337     src = ra_alloc1(as, ir->op2, LJ_SOFTFP ? RSET_GPR : RSET_FPR);
1338     idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
1339     emit_hsi(as, LJ_SOFTFP ? MIPSI_SD : MIPSI_SDC1, src, idx, ofs);
1340   } else {
1341 #if LJ_32
1342     if (!irt_ispri(ir->t)) {
1343       src = ra_alloc1(as, ir->op2, allow);
1344       rset_clear(allow, src);
1345     }
1346     if (LJ_SOFTFP && (ir+1)->o == IR_HIOP)
1347       type = ra_alloc1(as, (ir+1)->op2, allow);
1348     else
1349       type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
1350     rset_clear(allow, type);
1351     idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
1352     if (ra_hasreg(src))
1353       emit_tsi(as, MIPSI_SW, src, idx, ofs+(LJ_BE?4:0));
1354     emit_tsi(as, MIPSI_SW, type, idx, ofs+(LJ_BE?0:4));
1355 #else
1356     Reg tmp = RID_TMP;
1357     if (irt_ispri(ir->t)) {
1358       tmp = ra_allock(as, ~((int64_t)~irt_toitype(ir->t) << 47), allow);
1359       rset_clear(allow, tmp);
1360     } else {
1361       src = ra_alloc1(as, ir->op2, allow);
1362       rset_clear(allow, src);
1363       type = ra_allock(as, (int64_t)irt_toitype(ir->t) << 47, allow);
1364       rset_clear(allow, type);
1365     }
1366     idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
1367     emit_tsi(as, MIPSI_SD, tmp, idx, ofs);
1368     if (ra_hasreg(src)) {
1369       if (irt_isinteger(ir->t)) {
1370         emit_dst(as, MIPSI_DADDU, tmp, tmp, type);
1371         emit_tsml(as, MIPSI_DEXT, tmp, src, 31, 0);
1372       } else {
1373         emit_dst(as, MIPSI_DADDU, tmp, src, type);
1374       }
1375     }
1376 #endif
1377   }
1378 }
1379 
1380 static void asm_sload(ASMState *as, IRIns *ir)
1381 {
1382   Reg dest = RID_NONE, type = RID_NONE, base;
1383   RegSet allow = RSET_GPR;
1384   IRType1 t = ir->t;
1385 #if LJ_32
1386   int32_t ofs = 8*((int32_t)ir->op1-1) + ((ir->op2 & IRSLOAD_FRAME) ? 4 : 0);
1387   int hiop = (LJ_SOFTFP32 && (ir+1)->o == IR_HIOP);
1388   if (hiop)
1389     t.irt = IRT_NUM;
1390 #else
1391   int32_t ofs = 8*((int32_t)ir->op1-2);
1392 #endif
1393   lua_assert(!(ir->op2 & IRSLOAD_PARENT));  /* Handled by asm_head_side(). */
1394   lua_assert(irt_isguard(ir->t) || !(ir->op2 & IRSLOAD_TYPECHECK));
1395 #if LJ_SOFTFP32
1396   lua_assert(!(ir->op2 & IRSLOAD_CONVERT));  /* Handled by LJ_SOFTFP SPLIT. */
1397   if (hiop && ra_used(ir+1)) {
1398     type = ra_dest(as, ir+1, allow);
1399     rset_clear(allow, type);
1400   }
1401 #else
1402   if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t) && irt_isint(t)) {
1403     dest = ra_scratch(as, LJ_SOFTFP ? allow : RSET_FPR);
1404     asm_tointg(as, ir, dest);
1405     t.irt = IRT_NUM;  /* Continue with a regular number type check. */
1406   } else
1407 #endif
1408   if (ra_used(ir)) {
1409     lua_assert((LJ_SOFTFP32 ? 0 : irt_isnum(ir->t)) ||
1410                irt_isint(ir->t) || irt_isaddr(ir->t));
1411     dest = ra_dest(as, ir, (!LJ_SOFTFP && irt_isnum(t)) ? RSET_FPR : allow);
1412     rset_clear(allow, dest);
1413     base = ra_alloc1(as, REF_BASE, allow);
1414     rset_clear(allow, base);
1415     if (!LJ_SOFTFP32 && (ir->op2 & IRSLOAD_CONVERT)) {
1416       if (irt_isint(t)) {
1417         Reg tmp = ra_scratch(as, LJ_SOFTFP ? RSET_GPR : RSET_FPR);
1418 #if LJ_SOFTFP
1419         ra_evictset(as, rset_exclude(RSET_SCRATCH, dest));
1420         ra_destreg(as, ir, RID_RET);
1421         emit_call(as, (void *)lj_ir_callinfo[IRCALL_softfp_d2i].func, 0);
1422         if (tmp != REGARG_FIRSTGPR)
1423           emit_move(as, REGARG_FIRSTGPR, tmp);
1424 #else
1425         emit_tg(as, MIPSI_MFC1, dest, tmp);
1426         emit_fg(as, MIPSI_TRUNC_W_D, tmp, tmp);
1427 #endif
1428         dest = tmp;
1429         t.irt = IRT_NUM;  /* Check for original type. */
1430       } else {
1431         Reg tmp = ra_scratch(as, RSET_GPR);
1432 #if LJ_SOFTFP
1433         ra_evictset(as, rset_exclude(RSET_SCRATCH, dest));
1434         ra_destreg(as, ir, RID_RET);
1435         emit_call(as, (void *)lj_ir_callinfo[IRCALL_softfp_i2d].func, 0);
1436         emit_dta(as, MIPSI_SLL, REGARG_FIRSTGPR, tmp, 0);
1437 #else
1438         emit_fg(as, MIPSI_CVT_D_W, dest, dest);
1439         emit_tg(as, MIPSI_MTC1, tmp, dest);
1440 #endif
1441         dest = tmp;
1442         t.irt = IRT_INT;  /* Check for original type. */
1443       }
1444     }
1445 #if LJ_64
1446     else if (irt_isaddr(t)) {
1447       /* Clear type from pointers. */
1448       emit_tsml(as, MIPSI_DEXTM, dest, dest, 14, 0);
1449     } else if (irt_isint(t) && (ir->op2 & IRSLOAD_TYPECHECK)) {
1450       /* Sign-extend integers. */
1451       emit_dta(as, MIPSI_SLL, dest, dest, 0);
1452     }
1453 #endif
1454     goto dotypecheck;
1455   }
1456   base = ra_alloc1(as, REF_BASE, allow);
1457   rset_clear(allow, base);
1458 dotypecheck:
1459 #if LJ_32
1460   if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1461     if (ra_noreg(type))
1462       type = RID_TMP;
1463     if (irt_isnum(t)) {
1464       asm_guard(as, MIPSI_BEQ, RID_TMP, RID_ZERO);
1465       emit_tsi(as, MIPSI_SLTIU, RID_TMP, type, (int32_t)LJ_TISNUM);
1466     } else {
1467       Reg ktype = ra_allock(as, irt_toitype(t), allow);
1468       asm_guard(as, MIPSI_BNE, type, ktype);
1469     }
1470   }
1471   if (ra_hasreg(dest)) {
1472     if (!LJ_SOFTFP && irt_isnum(t))
1473       emit_hsi(as, MIPSI_LDC1, dest, base, ofs);
1474     else
1475       emit_tsi(as, MIPSI_LW, dest, base, ofs ^ (LJ_BE?4:0));
1476   }
1477   if (ra_hasreg(type))
1478     emit_tsi(as, MIPSI_LW, type, base, ofs ^ (LJ_BE?0:4));
1479 #else
1480   if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1481     type = dest < RID_MAX_GPR ? dest : RID_TMP;
1482     if (irt_ispri(t)) {
1483       asm_guard(as, MIPSI_BNE, type,
1484                 ra_allock(as, ~((int64_t)~irt_toitype(t) << 47) , allow));
1485     } else {
1486       if (irt_isnum(t)) {
1487         asm_guard(as, MIPSI_BEQ, RID_TMP, RID_ZERO);
1488         emit_tsi(as, MIPSI_SLTIU, RID_TMP, RID_TMP, (int32_t)LJ_TISNUM);
1489         if (!LJ_SOFTFP && ra_hasreg(dest))
1490           emit_hsi(as, MIPSI_LDC1, dest, base, ofs);
1491       } else {
1492         asm_guard(as, MIPSI_BNE, RID_TMP,
1493                   ra_allock(as, (int32_t)irt_toitype(t), allow));
1494       }
1495       emit_dta(as, MIPSI_DSRA32, RID_TMP, type, 15);
1496     }
1497     emit_tsi(as, MIPSI_LD, type, base, ofs);
1498   } else if (ra_hasreg(dest)) {
1499     if (!LJ_SOFTFP && irt_isnum(t))
1500       emit_hsi(as, MIPSI_LDC1, dest, base, ofs);
1501     else
1502       emit_tsi(as, irt_isint(t) ? MIPSI_LW : MIPSI_LD, dest, base,
1503                ofs ^ ((LJ_BE && irt_isint(t)) ? 4 : 0));
1504   }
1505 #endif
1506 }
1507 
1508 /* -- Allocations --------------------------------------------------------- */
1509 
1510 #if LJ_HASFFI
1511 static void asm_cnew(ASMState *as, IRIns *ir)
1512 {
1513   CTState *cts = ctype_ctsG(J2G(as->J));
1514   CTypeID id = (CTypeID)IR(ir->op1)->i;
1515   CTSize sz;
1516   CTInfo info = lj_ctype_info(cts, id, &sz);
1517   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
1518   IRRef args[4];
1519   RegSet drop = RSET_SCRATCH;
1520   lua_assert(sz != CTSIZE_INVALID || (ir->o == IR_CNEW && ir->op2 != REF_NIL));
1521 
1522   as->gcsteps++;
1523   if (ra_hasreg(ir->r))
1524     rset_clear(drop, ir->r);  /* Dest reg handled below. */
1525   ra_evictset(as, drop);
1526   if (ra_used(ir))
1527     ra_destreg(as, ir, RID_RET);  /* GCcdata * */
1528 
1529   /* Initialize immutable cdata object. */
1530   if (ir->o == IR_CNEWI) {
1531     RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
1532 #if LJ_32
1533     int32_t ofs = sizeof(GCcdata);
1534     if (sz == 8) {
1535       ofs += 4;
1536       lua_assert((ir+1)->o == IR_HIOP);
1537       if (LJ_LE) ir++;
1538     }
1539     for (;;) {
1540       Reg r = ra_alloc1z(as, ir->op2, allow);
1541       emit_tsi(as, MIPSI_SW, r, RID_RET, ofs);
1542       rset_clear(allow, r);
1543       if (ofs == sizeof(GCcdata)) break;
1544       ofs -= 4; if (LJ_BE) ir++; else ir--;
1545     }
1546 #else
1547     emit_tsi(as, MIPSI_SD, ra_alloc1(as, ir->op2, allow),
1548              RID_RET, sizeof(GCcdata));
1549 #endif
1550     lua_assert(sz == 4 || sz == 8);
1551   } else if (ir->op2 != REF_NIL) {  /* Create VLA/VLS/aligned cdata. */
1552     ci = &lj_ir_callinfo[IRCALL_lj_cdata_newv];
1553     args[0] = ASMREF_L;     /* lua_State *L */
1554     args[1] = ir->op1;      /* CTypeID id   */
1555     args[2] = ir->op2;      /* CTSize sz    */
1556     args[3] = ASMREF_TMP1;  /* CTSize align */
1557     asm_gencall(as, ci, args);
1558     emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)ctype_align(info));
1559     return;
1560   }
1561 
1562   /* Initialize gct and ctypeid. lj_mem_newgco() already sets marked. */
1563   emit_tsi(as, MIPSI_SB, RID_RET+1, RID_RET, offsetof(GCcdata, gct));
1564   emit_tsi(as, MIPSI_SH, RID_TMP, RID_RET, offsetof(GCcdata, ctypeid));
1565   emit_ti(as, MIPSI_LI, RID_RET+1, ~LJ_TCDATA);
1566   emit_ti(as, MIPSI_LI, RID_TMP, id); /* Lower 16 bit used. Sign-ext ok. */
1567   args[0] = ASMREF_L;     /* lua_State *L */
1568   args[1] = ASMREF_TMP1;  /* MSize size   */
1569   asm_gencall(as, ci, args);
1570   ra_allockreg(as, (int32_t)(sz+sizeof(GCcdata)),
1571                ra_releasetmp(as, ASMREF_TMP1));
1572 }
1573 #else
1574 #define asm_cnew(as, ir)        ((void)0)
1575 #endif
1576 
1577 /* -- Write barriers ------------------------------------------------------ */
1578 
1579 static void asm_tbar(ASMState *as, IRIns *ir)
1580 {
1581   Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
1582   Reg mark = ra_scratch(as, rset_exclude(RSET_GPR, tab));
1583   Reg link = RID_TMP;
1584   MCLabel l_end = emit_label(as);
1585   emit_tsi(as, MIPSI_AS, link, tab, (int32_t)offsetof(GCtab, gclist));
1586   emit_tsi(as, MIPSI_SB, mark, tab, (int32_t)offsetof(GCtab, marked));
1587   emit_setgl(as, tab, gc.grayagain);
1588   emit_getgl(as, link, gc.grayagain);
1589   emit_dst(as, MIPSI_XOR, mark, mark, RID_TMP);  /* Clear black bit. */
1590   emit_branch(as, MIPSI_BEQ, RID_TMP, RID_ZERO, l_end);
1591   emit_tsi(as, MIPSI_ANDI, RID_TMP, mark, LJ_GC_BLACK);
1592   emit_tsi(as, MIPSI_LBU, mark, tab, (int32_t)offsetof(GCtab, marked));
1593 }
1594 
1595 static void asm_obar(ASMState *as, IRIns *ir)
1596 {
1597   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
1598   IRRef args[2];
1599   MCLabel l_end;
1600   Reg obj, val, tmp;
1601   /* No need for other object barriers (yet). */
1602   lua_assert(IR(ir->op1)->o == IR_UREFC);
1603   ra_evictset(as, RSET_SCRATCH);
1604   l_end = emit_label(as);
1605   args[0] = ASMREF_TMP1;  /* global_State *g */
1606   args[1] = ir->op1;      /* TValue *tv      */
1607   asm_gencall(as, ci, args);
1608   emit_tsi(as, MIPSI_AADDIU, ra_releasetmp(as, ASMREF_TMP1), RID_JGL, -32768);
1609   obj = IR(ir->op1)->r;
1610   tmp = ra_scratch(as, rset_exclude(RSET_GPR, obj));
1611   emit_branch(as, MIPSI_BEQ, RID_TMP, RID_ZERO, l_end);
1612   emit_tsi(as, MIPSI_ANDI, tmp, tmp, LJ_GC_BLACK);
1613   emit_branch(as, MIPSI_BEQ, RID_TMP, RID_ZERO, l_end);
1614   emit_tsi(as, MIPSI_ANDI, RID_TMP, RID_TMP, LJ_GC_WHITES);
1615   val = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, obj));
1616   emit_tsi(as, MIPSI_LBU, tmp, obj,
1617            (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
1618   emit_tsi(as, MIPSI_LBU, RID_TMP, val, (int32_t)offsetof(GChead, marked));
1619 }
1620 
1621 /* -- Arithmetic and logic operations ------------------------------------- */
1622 
1623 #if !LJ_SOFTFP
1624 static void asm_fparith(ASMState *as, IRIns *ir, MIPSIns mi)
1625 {
1626   Reg dest = ra_dest(as, ir, RSET_FPR);
1627   Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1628   right = (left >> 8); left &= 255;
1629   emit_fgh(as, mi, dest, left, right);
1630 }
1631 
1632 static void asm_fpunary(ASMState *as, IRIns *ir, MIPSIns mi)
1633 {
1634   Reg dest = ra_dest(as, ir, RSET_FPR);
1635   Reg left = ra_hintalloc(as, ir->op1, dest, RSET_FPR);
1636   emit_fg(as, mi, dest, left);
1637 }
1638 #endif
1639 
1640 #if !LJ_SOFTFP32
1641 static void asm_fpmath(ASMState *as, IRIns *ir)
1642 {
1643   if (ir->op2 == IRFPM_EXP2 && asm_fpjoin_pow(as, ir))
1644     return;
1645 #if !LJ_SOFTFP
1646   if (ir->op2 <= IRFPM_TRUNC)
1647     asm_callround(as, ir, IRCALL_lj_vm_floor + ir->op2);
1648   else if (ir->op2 == IRFPM_SQRT)
1649     asm_fpunary(as, ir, MIPSI_SQRT_D);
1650   else
1651 #endif
1652     asm_callid(as, ir, IRCALL_lj_vm_floor + ir->op2);
1653 }
1654 #endif
1655 
1656 #if !LJ_SOFTFP
1657 #define asm_fpadd(as, ir)       asm_fparith(as, ir, MIPSI_ADD_D)
1658 #define asm_fpsub(as, ir)       asm_fparith(as, ir, MIPSI_SUB_D)
1659 #define asm_fpmul(as, ir)       asm_fparith(as, ir, MIPSI_MUL_D)
1660 #elif LJ_64  /* && LJ_SOFTFP */
1661 #define asm_fpadd(as, ir)       asm_callid(as, ir, IRCALL_softfp_add)
1662 #define asm_fpsub(as, ir)       asm_callid(as, ir, IRCALL_softfp_sub)
1663 #define asm_fpmul(as, ir)       asm_callid(as, ir, IRCALL_softfp_mul)
1664 #endif
1665 
1666 static void asm_add(ASMState *as, IRIns *ir)
1667 {
1668   IRType1 t = ir->t;
1669 #if !LJ_SOFTFP32
1670   if (irt_isnum(t)) {
1671     asm_fpadd(as, ir);
1672   } else
1673 #endif
1674   {
1675     Reg dest = ra_dest(as, ir, RSET_GPR);
1676     Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1677     if (irref_isk(ir->op2)) {
1678       intptr_t k = get_kval(IR(ir->op2));
1679       if (checki16(k)) {
1680         emit_tsi(as, (LJ_64 && irt_is64(t)) ? MIPSI_DADDIU : MIPSI_ADDIU, dest,
1681                  left, k);
1682         return;
1683       }
1684     }
1685     right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1686     emit_dst(as, (LJ_64 && irt_is64(t)) ? MIPSI_DADDU : MIPSI_ADDU, dest,
1687              left, right);
1688   }
1689 }
1690 
1691 static void asm_sub(ASMState *as, IRIns *ir)
1692 {
1693 #if !LJ_SOFTFP32
1694   if (irt_isnum(ir->t)) {
1695     asm_fpsub(as, ir);
1696   } else
1697 #endif
1698   {
1699     Reg dest = ra_dest(as, ir, RSET_GPR);
1700     Reg right, left = ra_alloc2(as, ir, RSET_GPR);
1701     right = (left >> 8); left &= 255;
1702     emit_dst(as, (LJ_64 && irt_is64(ir->t)) ? MIPSI_DSUBU : MIPSI_SUBU, dest,
1703              left, right);
1704   }
1705 }
1706 
1707 static void asm_mul(ASMState *as, IRIns *ir)
1708 {
1709 #if !LJ_SOFTFP32
1710   if (irt_isnum(ir->t)) {
1711     asm_fpmul(as, ir);
1712   } else
1713 #endif
1714   {
1715     Reg dest = ra_dest(as, ir, RSET_GPR);
1716     Reg right, left = ra_alloc2(as, ir, RSET_GPR);
1717     right = (left >> 8); left &= 255;
1718     if (LJ_64 && irt_is64(ir->t)) {
1719       emit_dst(as, MIPSI_MFLO, dest, 0, 0);
1720       emit_dst(as, MIPSI_DMULT, 0, left, right);
1721     } else {
1722       emit_dst(as, MIPSI_MUL, dest, left, right);
1723     }
1724   }
1725 }
1726 
1727 static void asm_mod(ASMState *as, IRIns *ir)
1728 {
1729 #if LJ_64 && LJ_HASFFI
1730   if (!irt_isint(ir->t))
1731     asm_callid(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_modi64 :
1732                                           IRCALL_lj_carith_modu64);
1733   else
1734 #endif
1735     asm_callid(as, ir, IRCALL_lj_vm_modi);
1736 }
1737 
1738 #if !LJ_SOFTFP32
1739 static void asm_pow(ASMState *as, IRIns *ir)
1740 {
1741 #if LJ_64 && LJ_HASFFI
1742   if (!irt_isnum(ir->t))
1743     asm_callid(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_powi64 :
1744                                           IRCALL_lj_carith_powu64);
1745   else
1746 #endif
1747     asm_callid(as, ir, IRCALL_lj_vm_powi);
1748 }
1749 
1750 static void asm_div(ASMState *as, IRIns *ir)
1751 {
1752 #if LJ_64 && LJ_HASFFI
1753   if (!irt_isnum(ir->t))
1754     asm_callid(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_divi64 :
1755                                           IRCALL_lj_carith_divu64);
1756   else
1757 #endif
1758 #if !LJ_SOFTFP
1759     asm_fparith(as, ir, MIPSI_DIV_D);
1760 #else
1761   asm_callid(as, ir, IRCALL_softfp_div);
1762 #endif
1763 }
1764 #endif
1765 
1766 static void asm_neg(ASMState *as, IRIns *ir)
1767 {
1768 #if !LJ_SOFTFP
1769   if (irt_isnum(ir->t)) {
1770     asm_fpunary(as, ir, MIPSI_NEG_D);
1771   } else
1772 #elif LJ_64  /* && LJ_SOFTFP */
1773   if (irt_isnum(ir->t)) {
1774     Reg dest = ra_dest(as, ir, RSET_GPR);
1775     Reg left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1776     emit_dst(as, MIPSI_XOR, dest, left,
1777             ra_allock(as, 0x8000000000000000ll, rset_exclude(RSET_GPR, dest)));
1778   } else
1779 #endif
1780   {
1781     Reg dest = ra_dest(as, ir, RSET_GPR);
1782     Reg left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1783     emit_dst(as, (LJ_64 && irt_is64(ir->t)) ? MIPSI_DSUBU : MIPSI_SUBU, dest,
1784              RID_ZERO, left);
1785   }
1786 }
1787 
1788 #if !LJ_SOFTFP
1789 #define asm_abs(as, ir)         asm_fpunary(as, ir, MIPSI_ABS_D)
1790 #elif LJ_64   /* && LJ_SOFTFP */
1791 static void asm_abs(ASMState *as, IRIns *ir)
1792 {
1793   Reg dest = ra_dest(as, ir, RSET_GPR);
1794   Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1795   emit_tsml(as, MIPSI_DEXTM, dest, left, 30, 0);
1796 }
1797 #endif
1798 
1799 #define asm_atan2(as, ir)       asm_callid(as, ir, IRCALL_atan2)
1800 #define asm_ldexp(as, ir)       asm_callid(as, ir, IRCALL_ldexp)
1801 
1802 static void asm_arithov(ASMState *as, IRIns *ir)
1803 {
1804   Reg right, left, tmp, dest = ra_dest(as, ir, RSET_GPR);
1805   lua_assert(!irt_is64(ir->t));
1806   if (irref_isk(ir->op2)) {
1807     int k = IR(ir->op2)->i;
1808     if (ir->o == IR_SUBOV) k = -k;
1809     if (checki16(k)) {  /* (dest < left) == (k >= 0 ? 1 : 0) */
1810       left = ra_alloc1(as, ir->op1, RSET_GPR);
1811       asm_guard(as, k >= 0 ? MIPSI_BNE : MIPSI_BEQ, RID_TMP, RID_ZERO);
1812       emit_dst(as, MIPSI_SLT, RID_TMP, dest, dest == left ? RID_TMP : left);
1813       emit_tsi(as, MIPSI_ADDIU, dest, left, k);
1814       if (dest == left) emit_move(as, RID_TMP, left);
1815       return;
1816     }
1817   }
1818   left = ra_alloc2(as, ir, RSET_GPR);
1819   right = (left >> 8); left &= 255;
1820   tmp = ra_scratch(as, rset_exclude(rset_exclude(rset_exclude(RSET_GPR, left),
1821                                                  right), dest));
1822   asm_guard(as, MIPSI_BLTZ, RID_TMP, 0);
1823   emit_dst(as, MIPSI_AND, RID_TMP, RID_TMP, tmp);
1824   if (ir->o == IR_ADDOV) {  /* ((dest^left) & (dest^right)) < 0 */
1825     emit_dst(as, MIPSI_XOR, RID_TMP, dest, dest == right ? RID_TMP : right);
1826   } else {  /* ((dest^left) & (dest^~right)) < 0 */
1827     emit_dst(as, MIPSI_XOR, RID_TMP, RID_TMP, dest);
1828     emit_dst(as, MIPSI_NOR, RID_TMP, dest == right ? RID_TMP : right, RID_ZERO);
1829   }
1830   emit_dst(as, MIPSI_XOR, tmp, dest, dest == left ? RID_TMP : left);
1831   emit_dst(as, ir->o == IR_ADDOV ? MIPSI_ADDU : MIPSI_SUBU, dest, left, right);
1832   if (dest == left || dest == right)
1833     emit_move(as, RID_TMP, dest == left ? left : right);
1834 }
1835 
1836 #define asm_addov(as, ir)       asm_arithov(as, ir)
1837 #define asm_subov(as, ir)       asm_arithov(as, ir)
1838 
1839 static void asm_mulov(ASMState *as, IRIns *ir)
1840 {
1841   Reg dest = ra_dest(as, ir, RSET_GPR);
1842   Reg tmp, right, left = ra_alloc2(as, ir, RSET_GPR);
1843   right = (left >> 8); left &= 255;
1844   tmp = ra_scratch(as, rset_exclude(rset_exclude(rset_exclude(RSET_GPR, left),
1845                                                  right), dest));
1846   asm_guard(as, MIPSI_BNE, RID_TMP, tmp);
1847   emit_dta(as, MIPSI_SRA, RID_TMP, dest, 31);
1848   emit_dst(as, MIPSI_MFHI, tmp, 0, 0);
1849   emit_dst(as, MIPSI_MFLO, dest, 0, 0);
1850   emit_dst(as, MIPSI_MULT, 0, left, right);
1851 }
1852 
1853 #if LJ_32 && LJ_HASFFI
1854 static void asm_add64(ASMState *as, IRIns *ir)
1855 {
1856   Reg dest = ra_dest(as, ir, RSET_GPR);
1857   Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
1858   if (irref_isk(ir->op2)) {
1859     int32_t k = IR(ir->op2)->i;
1860     if (k == 0) {
1861       emit_dst(as, MIPSI_ADDU, dest, left, RID_TMP);
1862       goto loarith;
1863     } else if (checki16(k)) {
1864       emit_dst(as, MIPSI_ADDU, dest, dest, RID_TMP);
1865       emit_tsi(as, MIPSI_ADDIU, dest, left, k);
1866       goto loarith;
1867     }
1868   }
1869   emit_dst(as, MIPSI_ADDU, dest, dest, RID_TMP);
1870   right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1871   emit_dst(as, MIPSI_ADDU, dest, left, right);
1872 loarith:
1873   ir--;
1874   dest = ra_dest(as, ir, RSET_GPR);
1875   left = ra_alloc1(as, ir->op1, RSET_GPR);
1876   if (irref_isk(ir->op2)) {
1877     int32_t k = IR(ir->op2)->i;
1878     if (k == 0) {
1879       if (dest != left)
1880         emit_move(as, dest, left);
1881       return;
1882     } else if (checki16(k)) {
1883       if (dest == left) {
1884         Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, left));
1885         emit_move(as, dest, tmp);
1886         dest = tmp;
1887       }
1888       emit_dst(as, MIPSI_SLTU, RID_TMP, dest, left);
1889       emit_tsi(as, MIPSI_ADDIU, dest, left, k);
1890       return;
1891     }
1892   }
1893   right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1894   if (dest == left && dest == right) {
1895     Reg tmp = ra_scratch(as, rset_exclude(rset_exclude(RSET_GPR, left), right));
1896     emit_move(as, dest, tmp);
1897     dest = tmp;
1898   }
1899   emit_dst(as, MIPSI_SLTU, RID_TMP, dest, dest == left ? right : left);
1900   emit_dst(as, MIPSI_ADDU, dest, left, right);
1901 }
1902 
1903 static void asm_sub64(ASMState *as, IRIns *ir)
1904 {
1905   Reg dest = ra_dest(as, ir, RSET_GPR);
1906   Reg right, left = ra_alloc2(as, ir, RSET_GPR);
1907   right = (left >> 8); left &= 255;
1908   emit_dst(as, MIPSI_SUBU, dest, dest, RID_TMP);
1909   emit_dst(as, MIPSI_SUBU, dest, left, right);
1910   ir--;
1911   dest = ra_dest(as, ir, RSET_GPR);
1912   left = ra_alloc2(as, ir, RSET_GPR);
1913   right = (left >> 8); left &= 255;
1914   if (dest == left) {
1915     Reg tmp = ra_scratch(as, rset_exclude(rset_exclude(RSET_GPR, left), right));
1916     emit_move(as, dest, tmp);
1917     dest = tmp;
1918   }
1919   emit_dst(as, MIPSI_SLTU, RID_TMP, left, dest);
1920   emit_dst(as, MIPSI_SUBU, dest, left, right);
1921 }
1922 
1923 static void asm_neg64(ASMState *as, IRIns *ir)
1924 {
1925   Reg dest = ra_dest(as, ir, RSET_GPR);
1926   Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1927   emit_dst(as, MIPSI_SUBU, dest, dest, RID_TMP);
1928   emit_dst(as, MIPSI_SUBU, dest, RID_ZERO, left);
1929   ir--;
1930   dest = ra_dest(as, ir, RSET_GPR);
1931   left = ra_alloc1(as, ir->op1, RSET_GPR);
1932   emit_dst(as, MIPSI_SLTU, RID_TMP, RID_ZERO, dest);
1933   emit_dst(as, MIPSI_SUBU, dest, RID_ZERO, left);
1934 }
1935 #endif
1936 
1937 static void asm_bnot(ASMState *as, IRIns *ir)
1938 {
1939   Reg left, right, dest = ra_dest(as, ir, RSET_GPR);
1940   IRIns *irl = IR(ir->op1);
1941   if (mayfuse(as, ir->op1) && irl->o == IR_BOR) {
1942     left = ra_alloc2(as, irl, RSET_GPR);
1943     right = (left >> 8); left &= 255;
1944   } else {
1945     left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1946     right = RID_ZERO;
1947   }
1948   emit_dst(as, MIPSI_NOR, dest, left, right);
1949 }
1950 
1951 static void asm_bswap(ASMState *as, IRIns *ir)
1952 {
1953   Reg dest = ra_dest(as, ir, RSET_GPR);
1954   Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1955 #if LJ_32
1956   if ((as->flags & JIT_F_MIPSXXR2)) {
1957     emit_dta(as, MIPSI_ROTR, dest, RID_TMP, 16);
1958     emit_dst(as, MIPSI_WSBH, RID_TMP, 0, left);
1959   } else {
1960     Reg tmp = ra_scratch(as, rset_exclude(rset_exclude(RSET_GPR, left), dest));
1961     emit_dst(as, MIPSI_OR, dest, dest, tmp);
1962     emit_dst(as, MIPSI_OR, dest, dest, RID_TMP);
1963     emit_tsi(as, MIPSI_ANDI, dest, dest, 0xff00);
1964     emit_dta(as, MIPSI_SLL, RID_TMP, RID_TMP, 8);
1965     emit_dta(as, MIPSI_SRL, dest, left, 8);
1966     emit_tsi(as, MIPSI_ANDI, RID_TMP, left, 0xff00);
1967     emit_dst(as, MIPSI_OR, tmp, tmp, RID_TMP);
1968     emit_dta(as, MIPSI_SRL, tmp, left, 24);
1969     emit_dta(as, MIPSI_SLL, RID_TMP, left, 24);
1970   }
1971 #else
1972   if (irt_is64(ir->t)) {
1973     emit_dst(as, MIPSI_DSHD, dest, 0, RID_TMP);
1974     emit_dst(as, MIPSI_DSBH, RID_TMP, 0, left);
1975   } else {
1976     emit_dta(as, MIPSI_ROTR, dest, RID_TMP, 16);
1977     emit_dst(as, MIPSI_WSBH, RID_TMP, 0, left);
1978   }
1979 #endif
1980 }
1981 
1982 static void asm_bitop(ASMState *as, IRIns *ir, MIPSIns mi, MIPSIns mik)
1983 {
1984   Reg dest = ra_dest(as, ir, RSET_GPR);
1985   Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1986   if (irref_isk(ir->op2)) {
1987     intptr_t k = get_kval(IR(ir->op2));
1988     if (checku16(k)) {
1989       emit_tsi(as, mik, dest, left, k);
1990       return;
1991     }
1992   }
1993   right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1994   emit_dst(as, mi, dest, left, right);
1995 }
1996 
1997 #define asm_band(as, ir)        asm_bitop(as, ir, MIPSI_AND, MIPSI_ANDI)
1998 #define asm_bor(as, ir)         asm_bitop(as, ir, MIPSI_OR, MIPSI_ORI)
1999 #define asm_bxor(as, ir)        asm_bitop(as, ir, MIPSI_XOR, MIPSI_XORI)
2000 
2001 static void asm_bitshift(ASMState *as, IRIns *ir, MIPSIns mi, MIPSIns mik)
2002 {
2003   Reg dest = ra_dest(as, ir, RSET_GPR);
2004   if (irref_isk(ir->op2)) {  /* Constant shifts. */
2005     uint32_t shift = (uint32_t)IR(ir->op2)->i;
2006     if (LJ_64 && irt_is64(ir->t)) mik |= (shift & 32) ? MIPSI_D32 : MIPSI_D;
2007     emit_dta(as, mik, dest, ra_hintalloc(as, ir->op1, dest, RSET_GPR),
2008              (shift & 31));
2009   } else {
2010     Reg right, left = ra_alloc2(as, ir, RSET_GPR);
2011     right = (left >> 8); left &= 255;
2012     if (LJ_64 && irt_is64(ir->t)) mi |= MIPSI_DV;
2013     emit_dst(as, mi, dest, right, left);  /* Shift amount is in rs. */
2014   }
2015 }
2016 
2017 #define asm_bshl(as, ir)        asm_bitshift(as, ir, MIPSI_SLLV, MIPSI_SLL)
2018 #define asm_bshr(as, ir)        asm_bitshift(as, ir, MIPSI_SRLV, MIPSI_SRL)
2019 #define asm_bsar(as, ir)        asm_bitshift(as, ir, MIPSI_SRAV, MIPSI_SRA)
2020 #define asm_brol(as, ir)        lua_assert(0)
2021 
2022 static void asm_bror(ASMState *as, IRIns *ir)
2023 {
2024   if (LJ_64 || (as->flags & JIT_F_MIPSXXR2)) {
2025     asm_bitshift(as, ir, MIPSI_ROTRV, MIPSI_ROTR);
2026   } else {
2027     Reg dest = ra_dest(as, ir, RSET_GPR);
2028     if (irref_isk(ir->op2)) {  /* Constant shifts. */
2029       uint32_t shift = (uint32_t)(IR(ir->op2)->i & 31);
2030       Reg left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
2031       emit_rotr(as, dest, left, RID_TMP, shift);
2032     } else {
2033       Reg right, left = ra_alloc2(as, ir, RSET_GPR);
2034       right = (left >> 8); left &= 255;
2035       emit_dst(as, MIPSI_OR, dest, dest, RID_TMP);
2036       emit_dst(as, MIPSI_SRLV, dest, right, left);
2037       emit_dst(as, MIPSI_SLLV, RID_TMP, RID_TMP, left);
2038       emit_dst(as, MIPSI_SUBU, RID_TMP, ra_allock(as, 32, RSET_GPR), right);
2039     }
2040   }
2041 }
2042 
2043 #if LJ_SOFTFP
2044 static void asm_sfpmin_max(ASMState *as, IRIns *ir)
2045 {
2046   CCallInfo ci = lj_ir_callinfo[(IROp)ir->o == IR_MIN ? IRCALL_lj_vm_sfmin : IRCALL_lj_vm_sfmax];
2047 #if LJ_64
2048   IRRef args[2];
2049   args[0] = ir->op1;
2050   args[1] = ir->op2;
2051 #else
2052   IRRef args[4];
2053   args[0^LJ_BE] = ir->op1;
2054   args[1^LJ_BE] = (ir+1)->op1;
2055   args[2^LJ_BE] = ir->op2;
2056   args[3^LJ_BE] = (ir+1)->op2;
2057 #endif
2058   asm_setupresult(as, ir, &ci);
2059   emit_call(as, (void *)ci.func, 0);
2060   ci.func = NULL;
2061   asm_gencall(as, &ci, args);
2062 }
2063 #endif
2064 
2065 static void asm_min_max(ASMState *as, IRIns *ir, int ismax)
2066 {
2067   if (!LJ_SOFTFP32 && irt_isnum(ir->t)) {
2068 #if LJ_SOFTFP
2069     asm_sfpmin_max(as, ir);
2070 #else
2071     Reg dest = ra_dest(as, ir, RSET_FPR);
2072     Reg right, left = ra_alloc2(as, ir, RSET_FPR);
2073     right = (left >> 8); left &= 255;
2074     if (dest == left) {
2075       emit_fg(as, MIPSI_MOVT_D, dest, right);
2076     } else {
2077       emit_fg(as, MIPSI_MOVF_D, dest, left);
2078       if (dest != right) emit_fg(as, MIPSI_MOV_D, dest, right);
2079     }
2080     emit_fgh(as, MIPSI_C_OLT_D, 0, ismax ? left : right, ismax ? right : left);
2081 #endif
2082   } else {
2083     Reg dest = ra_dest(as, ir, RSET_GPR);
2084     Reg right, left = ra_alloc2(as, ir, RSET_GPR);
2085     right = (left >> 8); left &= 255;
2086     if (dest == left) {
2087       emit_dst(as, MIPSI_MOVN, dest, right, RID_TMP);
2088     } else {
2089       emit_dst(as, MIPSI_MOVZ, dest, left, RID_TMP);
2090       if (dest != right) emit_move(as, dest, right);
2091     }
2092     emit_dst(as, MIPSI_SLT, RID_TMP,
2093              ismax ? left : right, ismax ? right : left);
2094   }
2095 }
2096 
2097 #define asm_min(as, ir)         asm_min_max(as, ir, 0)
2098 #define asm_max(as, ir)         asm_min_max(as, ir, 1)
2099 
2100 /* -- Comparisons --------------------------------------------------------- */
2101 
2102 #if LJ_SOFTFP
2103 /* SFP comparisons. */
2104 static void asm_sfpcomp(ASMState *as, IRIns *ir)
2105 {
2106   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_softfp_cmp];
2107   RegSet drop = RSET_SCRATCH;
2108   Reg r;
2109 #if LJ_64
2110   IRRef args[2];
2111   args[0] = ir->op1;
2112   args[1] = ir->op2;
2113 #else
2114   IRRef args[4];
2115   args[LJ_LE ? 0 : 1] = ir->op1; args[LJ_LE ? 1 : 0] = (ir+1)->op1;
2116   args[LJ_LE ? 2 : 3] = ir->op2; args[LJ_LE ? 3 : 2] = (ir+1)->op2;
2117 #endif
2118 
2119   for (r = REGARG_FIRSTGPR; r <= REGARG_FIRSTGPR+(LJ_64?1:3); r++) {
2120     if (!rset_test(as->freeset, r) &&
2121         regcost_ref(as->cost[r]) == args[r-REGARG_FIRSTGPR])
2122       rset_clear(drop, r);
2123   }
2124   ra_evictset(as, drop);
2125 
2126   asm_setupresult(as, ir, ci);
2127 
2128   switch ((IROp)ir->o) {
2129   case IR_LT:
2130     asm_guard(as, MIPSI_BGEZ, RID_RET, 0);
2131     break;
2132   case IR_ULT:
2133     asm_guard(as, MIPSI_BEQ, RID_RET, RID_TMP);
2134     emit_loadi(as, RID_TMP, 1);
2135     asm_guard(as, MIPSI_BEQ, RID_RET, RID_ZERO);
2136     break;
2137   case IR_GE:
2138     asm_guard(as, MIPSI_BEQ, RID_RET, RID_TMP);
2139     emit_loadi(as, RID_TMP, 2);
2140     asm_guard(as, MIPSI_BLTZ, RID_RET, 0);
2141     break;
2142   case IR_LE:
2143     asm_guard(as, MIPSI_BGTZ, RID_RET, 0);
2144     break;
2145   case IR_GT:
2146     asm_guard(as, MIPSI_BEQ, RID_RET, RID_TMP);
2147     emit_loadi(as, RID_TMP, 2);
2148     asm_guard(as, MIPSI_BLEZ, RID_RET, 0);
2149     break;
2150   case IR_UGE:
2151     asm_guard(as, MIPSI_BLTZ, RID_RET, 0);
2152     break;
2153   case IR_ULE:
2154     asm_guard(as, MIPSI_BEQ, RID_RET, RID_TMP);
2155     emit_loadi(as, RID_TMP, 1);
2156     break;
2157   case IR_UGT: case IR_ABC:
2158     asm_guard(as, MIPSI_BLEZ, RID_RET, 0);
2159     break;
2160   case IR_EQ: case IR_NE:
2161     asm_guard(as, (ir->o & 1) ? MIPSI_BEQ : MIPSI_BNE, RID_RET, RID_ZERO);
2162   default:
2163     break;
2164   }
2165   asm_gencall(as, ci, args);
2166 }
2167 #endif
2168 
2169 static void asm_comp(ASMState *as, IRIns *ir)
2170 {
2171   /* ORDER IR: LT GE LE GT  ULT UGE ULE UGT. */
2172   IROp op = ir->o;
2173   if (!LJ_SOFTFP32 && irt_isnum(ir->t)) {
2174 #if LJ_SOFTFP
2175     asm_sfpcomp(as, ir);
2176 #else
2177     Reg right, left = ra_alloc2(as, ir, RSET_FPR);
2178     right = (left >> 8); left &= 255;
2179     asm_guard(as, (op&1) ? MIPSI_BC1T : MIPSI_BC1F, 0, 0);
2180     emit_fgh(as, MIPSI_C_OLT_D + ((op&3) ^ ((op>>2)&1)), 0, left, right);
2181 #endif
2182   } else {
2183     Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
2184     if (op == IR_ABC) op = IR_UGT;
2185     if ((op&4) == 0 && irref_isk(ir->op2) && get_kval(IR(ir->op2)) == 0) {
2186       MIPSIns mi = (op&2) ? ((op&1) ? MIPSI_BLEZ : MIPSI_BGTZ) :
2187                             ((op&1) ? MIPSI_BLTZ : MIPSI_BGEZ);
2188       asm_guard(as, mi, left, 0);
2189     } else {
2190       if (irref_isk(ir->op2)) {
2191         intptr_t k = get_kval(IR(ir->op2));
2192         if ((op&2)) k++;
2193         if (checki16(k)) {
2194           asm_guard(as, (op&1) ? MIPSI_BNE : MIPSI_BEQ, RID_TMP, RID_ZERO);
2195           emit_tsi(as, (op&4) ? MIPSI_SLTIU : MIPSI_SLTI,
2196                    RID_TMP, left, k);
2197           return;
2198         }
2199       }
2200       right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
2201       asm_guard(as, ((op^(op>>1))&1) ? MIPSI_BNE : MIPSI_BEQ, RID_TMP, RID_ZERO);
2202       emit_dst(as, (op&4) ? MIPSI_SLTU : MIPSI_SLT,
2203                RID_TMP, (op&2) ? right : left, (op&2) ? left : right);
2204     }
2205   }
2206 }
2207 
2208 static void asm_equal(ASMState *as, IRIns *ir)
2209 {
2210   Reg right, left = ra_alloc2(as, ir, (!LJ_SOFTFP && irt_isnum(ir->t)) ?
2211                                        RSET_FPR : RSET_GPR);
2212   right = (left >> 8); left &= 255;
2213   if (!LJ_SOFTFP32 && irt_isnum(ir->t)) {
2214 #if LJ_SOFTFP
2215     asm_sfpcomp(as, ir);
2216 #else
2217     asm_guard(as, (ir->o & 1) ? MIPSI_BC1T : MIPSI_BC1F, 0, 0);
2218     emit_fgh(as, MIPSI_C_EQ_D, 0, left, right);
2219 #endif
2220   } else {
2221     asm_guard(as, (ir->o & 1) ? MIPSI_BEQ : MIPSI_BNE, left, right);
2222   }
2223 }
2224 
2225 #if LJ_32 && LJ_HASFFI
2226 /* 64 bit integer comparisons. */
2227 static void asm_comp64(ASMState *as, IRIns *ir)
2228 {
2229   /* ORDER IR: LT GE LE GT  ULT UGE ULE UGT. */
2230   IROp op = (ir-1)->o;
2231   MCLabel l_end;
2232   Reg rightlo, leftlo, righthi, lefthi = ra_alloc2(as, ir, RSET_GPR);
2233   righthi = (lefthi >> 8); lefthi &= 255;
2234   leftlo = ra_alloc2(as, ir-1,
2235                      rset_exclude(rset_exclude(RSET_GPR, lefthi), righthi));
2236   rightlo = (leftlo >> 8); leftlo &= 255;
2237   asm_guard(as, ((op^(op>>1))&1) ? MIPSI_BNE : MIPSI_BEQ, RID_TMP, RID_ZERO);
2238   l_end = emit_label(as);
2239   if (lefthi != righthi)
2240     emit_dst(as, (op&4) ? MIPSI_SLTU : MIPSI_SLT, RID_TMP,
2241              (op&2) ? righthi : lefthi, (op&2) ? lefthi : righthi);
2242   emit_dst(as, MIPSI_SLTU, RID_TMP,
2243            (op&2) ? rightlo : leftlo, (op&2) ? leftlo : rightlo);
2244   if (lefthi != righthi)
2245     emit_branch(as, MIPSI_BEQ, lefthi, righthi, l_end);
2246 }
2247 
2248 static void asm_comp64eq(ASMState *as, IRIns *ir)
2249 {
2250   Reg tmp, right, left = ra_alloc2(as, ir, RSET_GPR);
2251   right = (left >> 8); left &= 255;
2252   asm_guard(as, ((ir-1)->o & 1) ? MIPSI_BEQ : MIPSI_BNE, RID_TMP, RID_ZERO);
2253   tmp = ra_scratch(as, rset_exclude(rset_exclude(RSET_GPR, left), right));
2254   emit_dst(as, MIPSI_OR, RID_TMP, RID_TMP, tmp);
2255   emit_dst(as, MIPSI_XOR, tmp, left, right);
2256   left = ra_alloc2(as, ir-1, RSET_GPR);
2257   right = (left >> 8); left &= 255;
2258   emit_dst(as, MIPSI_XOR, RID_TMP, left, right);
2259 }
2260 #endif
2261 
2262 /* -- Support for 64 bit ops in 32 bit mode ------------------------------- */
2263 
2264 /* Hiword op of a split 64 bit op. Previous op must be the loword op. */
2265 static void asm_hiop(ASMState *as, IRIns *ir)
2266 {
2267 #if LJ_32 && (LJ_HASFFI || LJ_SOFTFP)
2268   /* HIOP is marked as a store because it needs its own DCE logic. */
2269   int uselo = ra_used(ir-1), usehi = ra_used(ir);  /* Loword/hiword used? */
2270   if (LJ_UNLIKELY(!(as->flags & JIT_F_OPT_DCE))) uselo = usehi = 1;
2271   if ((ir-1)->o == IR_CONV) {  /* Conversions to/from 64 bit. */
2272     as->curins--;  /* Always skip the CONV. */
2273 #if LJ_HASFFI && !LJ_SOFTFP
2274     if (usehi || uselo)
2275       asm_conv64(as, ir);
2276     return;
2277 #endif
2278   } else if ((ir-1)->o < IR_EQ) {  /* 64 bit integer comparisons. ORDER IR. */
2279     as->curins--;  /* Always skip the loword comparison. */
2280 #if LJ_SOFTFP
2281     if (!irt_isint(ir->t)) {
2282       asm_sfpcomp(as, ir-1);
2283       return;
2284     }
2285 #endif
2286 #if LJ_HASFFI
2287     asm_comp64(as, ir);
2288 #endif
2289     return;
2290   } else if ((ir-1)->o <= IR_NE) {  /* 64 bit integer comparisons. ORDER IR. */
2291     as->curins--;  /* Always skip the loword comparison. */
2292 #if LJ_SOFTFP
2293     if (!irt_isint(ir->t)) {
2294       asm_sfpcomp(as, ir-1);
2295       return;
2296     }
2297 #endif
2298 #if LJ_HASFFI
2299     asm_comp64eq(as, ir);
2300 #endif
2301     return;
2302 #if LJ_SOFTFP
2303   } else if ((ir-1)->o == IR_MIN || (ir-1)->o == IR_MAX) {
2304       as->curins--;  /* Always skip the loword min/max. */
2305     if (uselo || usehi)
2306       asm_sfpmin_max(as, ir-1);
2307     return;
2308 #endif
2309   } else if ((ir-1)->o == IR_XSTORE) {
2310     as->curins--;  /* Handle both stores here. */
2311     if ((ir-1)->r != RID_SINK) {
2312       asm_xstore_(as, ir, LJ_LE ? 4 : 0);
2313       asm_xstore_(as, ir-1, LJ_LE ? 0 : 4);
2314     }
2315     return;
2316   }
2317   if (!usehi) return;  /* Skip unused hiword op for all remaining ops. */
2318   switch ((ir-1)->o) {
2319 #if LJ_HASFFI
2320   case IR_ADD: as->curins--; asm_add64(as, ir); break;
2321   case IR_SUB: as->curins--; asm_sub64(as, ir); break;
2322   case IR_NEG: as->curins--; asm_neg64(as, ir); break;
2323 #endif
2324 #if LJ_SOFTFP
2325   case IR_SLOAD: case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
2326   case IR_STRTO:
2327     if (!uselo)
2328       ra_allocref(as, ir->op1, RSET_GPR);  /* Mark lo op as used. */
2329     break;
2330 #endif
2331   case IR_CALLN:
2332   case IR_CALLS:
2333   case IR_CALLXS:
2334     if (!uselo)
2335       ra_allocref(as, ir->op1, RID2RSET(RID_RETLO));  /* Mark lo op as used. */
2336     break;
2337 #if LJ_SOFTFP
2338   case IR_ASTORE: case IR_HSTORE: case IR_USTORE: case IR_TOSTR:
2339 #endif
2340   case IR_CNEWI:
2341     /* Nothing to do here. Handled by lo op itself. */
2342     break;
2343   default: lua_assert(0); break;
2344   }
2345 #else
2346   UNUSED(as); UNUSED(ir); lua_assert(0);  /* Unused without FFI. */
2347 #endif
2348 }
2349 
2350 /* -- Profiling ----------------------------------------------------------- */
2351 
2352 static void asm_prof(ASMState *as, IRIns *ir)
2353 {
2354   UNUSED(ir);
2355   asm_guard(as, MIPSI_BNE, RID_TMP, RID_ZERO);
2356   emit_tsi(as, MIPSI_ANDI, RID_TMP, RID_TMP, HOOK_PROFILE);
2357   emit_lsglptr(as, MIPSI_LBU, RID_TMP,
2358                (int32_t)offsetof(global_State, hookmask));
2359 }
2360 
2361 /* -- Stack handling ------------------------------------------------------ */
2362 
2363 /* Check Lua stack size for overflow. Use exit handler as fallback. */
2364 static void asm_stack_check(ASMState *as, BCReg topslot,
2365                             IRIns *irp, RegSet allow, ExitNo exitno)
2366 {
2367   /* Try to get an unused temp. register, otherwise spill/restore RID_RET*. */
2368   Reg tmp, pbase = irp ? (ra_hasreg(irp->r) ? irp->r : RID_TMP) : RID_BASE;
2369   ExitNo oldsnap = as->snapno;
2370   rset_clear(allow, pbase);
2371 #if LJ_32
2372   tmp = allow ? rset_pickbot(allow) :
2373                 (pbase == RID_RETHI ? RID_RETLO : RID_RETHI);
2374 #else
2375   tmp = allow ? rset_pickbot(allow) : RID_RET;
2376 #endif
2377   as->snapno = exitno;
2378   asm_guard(as, MIPSI_BNE, RID_TMP, RID_ZERO);
2379   as->snapno = oldsnap;
2380   if (allow == RSET_EMPTY)  /* Restore temp. register. */
2381     emit_tsi(as, MIPSI_AL, tmp, RID_SP, 0);
2382   else
2383     ra_modified(as, tmp);
2384   emit_tsi(as, MIPSI_SLTIU, RID_TMP, RID_TMP, (int32_t)(8*topslot));
2385   emit_dst(as, MIPSI_ASUBU, RID_TMP, tmp, pbase);
2386   emit_tsi(as, MIPSI_AL, tmp, tmp, offsetof(lua_State, maxstack));
2387   if (pbase == RID_TMP)
2388     emit_getgl(as, RID_TMP, jit_base);
2389   emit_getgl(as, tmp, cur_L);
2390   if (allow == RSET_EMPTY)  /* Spill temp. register. */
2391     emit_tsi(as, MIPSI_AS, tmp, RID_SP, 0);
2392 }
2393 
2394 /* Restore Lua stack from on-trace state. */
2395 static void asm_stack_restore(ASMState *as, SnapShot *snap)
2396 {
2397   SnapEntry *map = &as->T->snapmap[snap->mapofs];
2398 #if LJ_32 || defined(LUA_USE_ASSERT)
2399   SnapEntry *flinks = &as->T->snapmap[snap_nextofs(as->T, snap)-1-LJ_FR2];
2400 #endif
2401   MSize n, nent = snap->nent;
2402   /* Store the value of all modified slots to the Lua stack. */
2403   for (n = 0; n < nent; n++) {
2404     SnapEntry sn = map[n];
2405     BCReg s = snap_slot(sn);
2406     int32_t ofs = 8*((int32_t)s-1-LJ_FR2);
2407     IRRef ref = snap_ref(sn);
2408     IRIns *ir = IR(ref);
2409     if ((sn & SNAP_NORESTORE))
2410       continue;
2411     if (irt_isnum(ir->t)) {
2412 #if LJ_SOFTFP32
2413       Reg tmp;
2414       RegSet allow = rset_exclude(RSET_GPR, RID_BASE);
2415       lua_assert(irref_isk(ref));  /* LJ_SOFTFP: must be a number constant. */
2416       tmp = ra_allock(as, (int32_t)ir_knum(ir)->u32.lo, allow);
2417       emit_tsi(as, MIPSI_SW, tmp, RID_BASE, ofs+(LJ_BE?4:0));
2418       if (rset_test(as->freeset, tmp+1)) allow = RID2RSET(tmp+1);
2419       tmp = ra_allock(as, (int32_t)ir_knum(ir)->u32.hi, allow);
2420       emit_tsi(as, MIPSI_SW, tmp, RID_BASE, ofs+(LJ_BE?0:4));
2421 #elif LJ_SOFTFP  /* && LJ_64 */
2422       Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, RID_BASE));
2423       emit_tsi(as, MIPSI_SD, src, RID_BASE, ofs);
2424 #else
2425       Reg src = ra_alloc1(as, ref, RSET_FPR);
2426       emit_hsi(as, MIPSI_SDC1, src, RID_BASE, ofs);
2427 #endif
2428     } else {
2429 #if LJ_32
2430       RegSet allow = rset_exclude(RSET_GPR, RID_BASE);
2431       Reg type;
2432       lua_assert(irt_ispri(ir->t) || irt_isaddr(ir->t) || irt_isinteger(ir->t));
2433       if (!irt_ispri(ir->t)) {
2434         Reg src = ra_alloc1(as, ref, allow);
2435         rset_clear(allow, src);
2436         emit_tsi(as, MIPSI_SW, src, RID_BASE, ofs+(LJ_BE?4:0));
2437       }
2438       if ((sn & (SNAP_CONT|SNAP_FRAME))) {
2439         if (s == 0) continue;  /* Do not overwrite link to previous frame. */
2440         type = ra_allock(as, (int32_t)(*flinks--), allow);
2441 #if LJ_SOFTFP
2442       } else if ((sn & SNAP_SOFTFPNUM)) {
2443         type = ra_alloc1(as, ref+1, rset_exclude(RSET_GPR, RID_BASE));
2444 #endif
2445       } else {
2446         type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
2447       }
2448       emit_tsi(as, MIPSI_SW, type, RID_BASE, ofs+(LJ_BE?0:4));
2449 #else
2450       asm_tvstore64(as, RID_BASE, ofs, ref);
2451 #endif
2452     }
2453     checkmclim(as);
2454   }
2455   lua_assert(map + nent == flinks);
2456 }
2457 
2458 /* -- GC handling --------------------------------------------------------- */
2459 
2460 /* Check GC threshold and do one or more GC steps. */
2461 static void asm_gc_check(ASMState *as)
2462 {
2463   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
2464   IRRef args[2];
2465   MCLabel l_end;
2466   Reg tmp;
2467   ra_evictset(as, RSET_SCRATCH);
2468   l_end = emit_label(as);
2469   /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
2470   /* Assumes asm_snap_prep() already done. */
2471   asm_guard(as, MIPSI_BNE, RID_RET, RID_ZERO);
2472   args[0] = ASMREF_TMP1;  /* global_State *g */
2473   args[1] = ASMREF_TMP2;  /* MSize steps     */
2474   asm_gencall(as, ci, args);
2475   emit_tsi(as, MIPSI_AADDIU, ra_releasetmp(as, ASMREF_TMP1), RID_JGL, -32768);
2476   tmp = ra_releasetmp(as, ASMREF_TMP2);
2477   emit_loadi(as, tmp, as->gcsteps);
2478   /* Jump around GC step if GC total < GC threshold. */
2479   emit_branch(as, MIPSI_BNE, RID_TMP, RID_ZERO, l_end);
2480   emit_dst(as, MIPSI_SLTU, RID_TMP, RID_TMP, tmp);
2481   emit_getgl(as, tmp, gc.threshold);
2482   emit_getgl(as, RID_TMP, gc.total);
2483   as->gcsteps = 0;
2484   checkmclim(as);
2485 }
2486 
2487 /* -- Loop handling ------------------------------------------------------- */
2488 
2489 /* Fixup the loop branch. */
2490 static void asm_loop_fixup(ASMState *as)
2491 {
2492   MCode *p = as->mctop;
2493   MCode *target = as->mcp;
2494   p[-1] = MIPSI_NOP;
2495   if (as->loopinv) {  /* Inverted loop branch? */
2496     /* asm_guard already inverted the cond branch. Only patch the target. */
2497     p[-3] |= ((target-p+2) & 0x0000ffffu);
2498   } else {
2499     p[-2] = MIPSI_J|(((uintptr_t)target>>2)&0x03ffffffu);
2500   }
2501 }
2502 
2503 /* -- Head of trace ------------------------------------------------------- */
2504 
2505 /* Coalesce BASE register for a root trace. */
2506 static void asm_head_root_base(ASMState *as)
2507 {
2508   IRIns *ir = IR(REF_BASE);
2509   Reg r = ir->r;
2510   if (as->loopinv) as->mctop--;
2511   if (ra_hasreg(r)) {
2512     ra_free(as, r);
2513     if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2514       ir->r = RID_INIT;  /* No inheritance for modified BASE register. */
2515     if (r != RID_BASE)
2516       emit_move(as, r, RID_BASE);
2517   }
2518 }
2519 
2520 /* Coalesce BASE register for a side trace. */
2521 static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
2522 {
2523   IRIns *ir = IR(REF_BASE);
2524   Reg r = ir->r;
2525   if (as->loopinv) as->mctop--;
2526   if (ra_hasreg(r)) {
2527     ra_free(as, r);
2528     if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2529       ir->r = RID_INIT;  /* No inheritance for modified BASE register. */
2530     if (irp->r == r) {
2531       rset_clear(allow, r);  /* Mark same BASE register as coalesced. */
2532     } else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
2533       rset_clear(allow, irp->r);
2534       emit_move(as, r, irp->r);  /* Move from coalesced parent reg. */
2535     } else {
2536       emit_getgl(as, r, jit_base);  /* Otherwise reload BASE. */
2537     }
2538   }
2539   return allow;
2540 }
2541 
2542 /* -- Tail of trace ------------------------------------------------------- */
2543 
2544 /* Fixup the tail code. */
2545 static void asm_tail_fixup(ASMState *as, TraceNo lnk)
2546 {
2547   MCode *target = lnk ? traceref(as->J,lnk)->mcode : (MCode *)lj_vm_exit_interp;
2548   int32_t spadj = as->T->spadjust;
2549   MCode *p = as->mctop-1;
2550   *p = spadj ? (MIPSI_AADDIU|MIPSF_T(RID_SP)|MIPSF_S(RID_SP)|spadj) : MIPSI_NOP;
2551   p[-1] = MIPSI_J|(((uintptr_t)target>>2)&0x03ffffffu);
2552 }
2553 
2554 /* Prepare tail of code. */
2555 static void asm_tail_prep(ASMState *as)
2556 {
2557   as->mcp = as->mctop-2;  /* Leave room for branch plus nop or stack adj. */
2558   as->invmcp = as->loopref ? as->mcp : NULL;
2559 }
2560 
2561 /* -- Trace setup --------------------------------------------------------- */
2562 
2563 /* Ensure there are enough stack slots for call arguments. */
2564 static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
2565 {
2566   IRRef args[CCI_NARGS_MAX*2];
2567   uint32_t i, nargs = CCI_XNARGS(ci);
2568 #if LJ_32
2569   int nslots = 4, ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
2570 #else
2571   int nslots = 0, ngpr = REGARG_NUMGPR;
2572 #endif
2573   asm_collectargs(as, ir, ci, args);
2574   for (i = 0; i < nargs; i++) {
2575 #if LJ_32
2576     if (!LJ_SOFTFP && args[i] && irt_isfp(IR(args[i])->t) &&
2577         nfpr > 0 && !(ci->flags & CCI_VARARG)) {
2578       nfpr--;
2579       ngpr -= irt_isnum(IR(args[i])->t) ? 2 : 1;
2580     } else if (!LJ_SOFTFP && args[i] && irt_isnum(IR(args[i])->t)) {
2581       nfpr = 0;
2582       ngpr = ngpr & ~1;
2583       if (ngpr > 0) ngpr -= 2; else nslots = (nslots+3) & ~1;
2584     } else {
2585       nfpr = 0;
2586       if (ngpr > 0) ngpr--; else nslots++;
2587     }
2588 #else
2589     if (ngpr > 0) ngpr--; else nslots += 2;
2590 #endif
2591   }
2592   if (nslots > as->evenspill)  /* Leave room for args in stack slots. */
2593     as->evenspill = nslots;
2594   return irt_isfp(ir->t) ? REGSP_HINT(RID_FPRET) : REGSP_HINT(RID_RET);
2595 }
2596 
2597 static void asm_setup_target(ASMState *as)
2598 {
2599   asm_sparejump_setup(as);
2600   asm_exitstub_setup(as);
2601 }
2602 
2603 /* -- Trace patching ------------------------------------------------------ */
2604 
2605 /* Patch exit jumps of existing machine code to a new target. */
2606 void lj_asm_patchexit(jit_State *J, GCtrace *T, ExitNo exitno, MCode *target)
2607 {
2608   MCode *p = T->mcode;
2609   MCode *pe = (MCode *)((char *)p + T->szmcode);
2610   MCode *px = exitstub_trace_addr(T, exitno);
2611   MCode *cstart = NULL, *cstop = NULL;
2612   MCode *mcarea = lj_mcode_patch(J, p, 0);
2613   MCode exitload = MIPSI_LI | MIPSF_T(RID_TMP) | exitno;
2614   MCode tjump = MIPSI_J|(((uintptr_t)target>>2)&0x03ffffffu);
2615   for (p++; p < pe; p++) {
2616     if (*p == exitload) {  /* Look for load of exit number. */
2617       /* Look for exitstub branch. Yes, this covers all used branch variants. */
2618       if (((p[-1] ^ (px-p)) & 0xffffu) == 0 &&
2619           ((p[-1] & 0xf0000000u) == MIPSI_BEQ ||
2620            (p[-1] & 0xfc1e0000u) == MIPSI_BLTZ ||
2621            (p[-1] & 0xffe00000u) == MIPSI_BC1F)) {
2622         ptrdiff_t delta = target - p;
2623         if (((delta + 0x8000) >> 16) == 0) {  /* Patch in-range branch. */
2624         patchbranch:
2625           p[-1] = (p[-1] & 0xffff0000u) | (delta & 0xffffu);
2626           *p = MIPSI_NOP;  /* Replace the load of the exit number. */
2627           cstop = p;
2628           if (!cstart) cstart = p-1;
2629         } else {  /* Branch out of range. Use spare jump slot in mcarea. */
2630           int i;
2631           for (i = (int)(sizeof(MCLink)/sizeof(MCode));
2632                i < (int)(sizeof(MCLink)/sizeof(MCode)+MIPS_SPAREJUMP*2);
2633                i += 2) {
2634             if (mcarea[i] == tjump) {
2635               delta = mcarea+i - p;
2636               goto patchbranch;
2637             } else if (mcarea[i] == MIPSI_NOP) {
2638               mcarea[i] = tjump;
2639               cstart = mcarea+i;
2640               delta = mcarea+i - p;
2641               goto patchbranch;
2642             }
2643           }
2644           /* Ignore jump slot overflow. Child trace is simply not attached. */
2645         }
2646       } else if (p+1 == pe) {
2647         /* Patch NOP after code for inverted loop branch. Use of J is ok. */
2648         lua_assert(p[1] == MIPSI_NOP);
2649         p[1] = tjump;
2650         *p = MIPSI_NOP;  /* Replace the load of the exit number. */
2651         cstop = p+2;
2652         if (!cstart) cstart = p+1;
2653       }
2654     }
2655   }
2656   if (cstart) lj_mcode_sync(cstart, cstop);
2657   lj_mcode_patch(J, mcarea, 1);
2658 }
2659 

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