root/lj_asm_ppc.h

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INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. ra_hintalloc
  2. ra_alloc2
  3. asm_exitstub_setup
  4. asm_exitstub_addr
  5. asm_guardcc
  6. noconflict
  7. asm_fuseabase
  8. asm_fuseahuref
  9. asm_fusexref
  10. asm_fusexrefx
  11. asm_fusemadd
  12. asm_gencall
  13. asm_setupresult
  14. asm_callx
  15. asm_retf
  16. asm_tointg
  17. asm_tobit
  18. asm_conv
  19. asm_strto
  20. asm_tvptr
  21. asm_aref
  22. asm_href
  23. asm_hrefk
  24. asm_uref
  25. asm_fref
  26. asm_strref
  27. asm_fxloadins
  28. asm_fxstoreins
  29. asm_fload
  30. asm_fstore
  31. asm_xload
  32. asm_xstore_
  33. asm_ahuvload
  34. asm_ahustore
  35. asm_sload
  36. asm_cnew
  37. asm_tbar
  38. asm_obar
  39. asm_fparith
  40. asm_fpunary
  41. asm_fpmath
  42. asm_add
  43. asm_sub
  44. asm_mul
  45. asm_neg
  46. asm_arithov
  47. asm_add64
  48. asm_sub64
  49. asm_neg64
  50. asm_bnot
  51. asm_bswap
  52. asm_fuseandsh
  53. asm_band
  54. asm_bitop
  55. asm_bitshift
  56. asm_sfpmin_max
  57. asm_min_max
  58. asm_intcomp_
  59. asm_comp
  60. asm_sfpcomp
  61. asm_comp64
  62. asm_hiop
  63. asm_prof
  64. asm_stack_check
  65. asm_stack_restore
  66. asm_gc_check
  67. asm_loop_fixup
  68. asm_head_root_base
  69. asm_head_side_base
  70. asm_tail_fixup
  71. asm_tail_prep
  72. asm_setup_call_slots
  73. asm_setup_target
  74. lj_asm_patchexit

   1 /*
   2 ** PPC IR assembler (SSA IR -> machine code).
   3 ** Copyright (C) 2005-2017 Mike Pall. See Copyright Notice in luajit.h
   4 */
   5 
   6 /* -- Register allocator extensions --------------------------------------- */
   7 
   8 /* Allocate a register with a hint. */
   9 static Reg ra_hintalloc(ASMState *as, IRRef ref, Reg hint, RegSet allow)
  10 {
  11   Reg r = IR(ref)->r;
  12   if (ra_noreg(r)) {
  13     if (!ra_hashint(r) && !iscrossref(as, ref))
  14       ra_sethint(IR(ref)->r, hint);  /* Propagate register hint. */
  15     r = ra_allocref(as, ref, allow);
  16   }
  17   ra_noweak(as, r);
  18   return r;
  19 }
  20 
  21 /* Allocate two source registers for three-operand instructions. */
  22 static Reg ra_alloc2(ASMState *as, IRIns *ir, RegSet allow)
  23 {
  24   IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
  25   Reg left = irl->r, right = irr->r;
  26   if (ra_hasreg(left)) {
  27     ra_noweak(as, left);
  28     if (ra_noreg(right))
  29       right = ra_allocref(as, ir->op2, rset_exclude(allow, left));
  30     else
  31       ra_noweak(as, right);
  32   } else if (ra_hasreg(right)) {
  33     ra_noweak(as, right);
  34     left = ra_allocref(as, ir->op1, rset_exclude(allow, right));
  35   } else if (ra_hashint(right)) {
  36     right = ra_allocref(as, ir->op2, allow);
  37     left = ra_alloc1(as, ir->op1, rset_exclude(allow, right));
  38   } else {
  39     left = ra_allocref(as, ir->op1, allow);
  40     right = ra_alloc1(as, ir->op2, rset_exclude(allow, left));
  41   }
  42   return left | (right << 8);
  43 }
  44 
  45 /* -- Guard handling ------------------------------------------------------ */
  46 
  47 /* Setup exit stubs after the end of each trace. */
  48 static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
  49 {
  50   ExitNo i;
  51   MCode *mxp = as->mctop;
  52   if (mxp - (nexits + 3 + MCLIM_REDZONE) < as->mclim)
  53     asm_mclimit(as);
  54   /* 1: mflr r0; bl ->vm_exit_handler; li r0, traceno; bl <1; bl <1; ... */
  55   for (i = nexits-1; (int32_t)i >= 0; i--)
  56     *--mxp = PPCI_BL|(((-3-i)&0x00ffffffu)<<2);
  57   *--mxp = PPCI_LI|PPCF_T(RID_TMP)|as->T->traceno;  /* Read by exit handler. */
  58   mxp--;
  59   *mxp = PPCI_BL|((((MCode *)(void *)lj_vm_exit_handler-mxp)&0x00ffffffu)<<2);
  60   *--mxp = PPCI_MFLR|PPCF_T(RID_TMP);
  61   as->mctop = mxp;
  62 }
  63 
  64 static MCode *asm_exitstub_addr(ASMState *as, ExitNo exitno)
  65 {
  66   /* Keep this in-sync with exitstub_trace_addr(). */
  67   return as->mctop + exitno + 3;
  68 }
  69 
  70 /* Emit conditional branch to exit for guard. */
  71 static void asm_guardcc(ASMState *as, PPCCC cc)
  72 {
  73   MCode *target = asm_exitstub_addr(as, as->snapno);
  74   MCode *p = as->mcp;
  75   if (LJ_UNLIKELY(p == as->invmcp)) {
  76     as->loopinv = 1;
  77     *p = PPCI_B | (((target-p) & 0x00ffffffu) << 2);
  78     emit_condbranch(as, PPCI_BC, cc^4, p);
  79     return;
  80   }
  81   emit_condbranch(as, PPCI_BC, cc, target);
  82 }
  83 
  84 /* -- Operand fusion ------------------------------------------------------ */
  85 
  86 /* Limit linear search to this distance. Avoids O(n^2) behavior. */
  87 #define CONFLICT_SEARCH_LIM     31
  88 
  89 /* Check if there's no conflicting instruction between curins and ref. */
  90 static int noconflict(ASMState *as, IRRef ref, IROp conflict)
  91 {
  92   IRIns *ir = as->ir;
  93   IRRef i = as->curins;
  94   if (i > ref + CONFLICT_SEARCH_LIM)
  95     return 0;  /* Give up, ref is too far away. */
  96   while (--i > ref)
  97     if (ir[i].o == conflict)
  98       return 0;  /* Conflict found. */
  99   return 1;  /* Ok, no conflict. */
 100 }
 101 
 102 /* Fuse the array base of colocated arrays. */
 103 static int32_t asm_fuseabase(ASMState *as, IRRef ref)
 104 {
 105   IRIns *ir = IR(ref);
 106   if (ir->o == IR_TNEW && ir->op1 <= LJ_MAX_COLOSIZE &&
 107       !neverfuse(as) && noconflict(as, ref, IR_NEWREF))
 108     return (int32_t)sizeof(GCtab);
 109   return 0;
 110 }
 111 
 112 /* Indicates load/store indexed is ok. */
 113 #define AHUREF_LSX      ((int32_t)0x80000000)
 114 
 115 /* Fuse array/hash/upvalue reference into register+offset operand. */
 116 static Reg asm_fuseahuref(ASMState *as, IRRef ref, int32_t *ofsp, RegSet allow)
 117 {
 118   IRIns *ir = IR(ref);
 119   if (ra_noreg(ir->r)) {
 120     if (ir->o == IR_AREF) {
 121       if (mayfuse(as, ref)) {
 122         if (irref_isk(ir->op2)) {
 123           IRRef tab = IR(ir->op1)->op1;
 124           int32_t ofs = asm_fuseabase(as, tab);
 125           IRRef refa = ofs ? tab : ir->op1;
 126           ofs += 8*IR(ir->op2)->i;
 127           if (checki16(ofs)) {
 128             *ofsp = ofs;
 129             return ra_alloc1(as, refa, allow);
 130           }
 131         }
 132         if (*ofsp == AHUREF_LSX) {
 133           Reg base = ra_alloc1(as, ir->op1, allow);
 134           Reg idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
 135           return base | (idx << 8);
 136         }
 137       }
 138     } else if (ir->o == IR_HREFK) {
 139       if (mayfuse(as, ref)) {
 140         int32_t ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
 141         if (checki16(ofs)) {
 142           *ofsp = ofs;
 143           return ra_alloc1(as, ir->op1, allow);
 144         }
 145       }
 146     } else if (ir->o == IR_UREFC) {
 147       if (irref_isk(ir->op1)) {
 148         GCfunc *fn = ir_kfunc(IR(ir->op1));
 149         int32_t ofs = i32ptr(&gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.tv);
 150         int32_t jgl = (intptr_t)J2G(as->J);
 151         if ((uint32_t)(ofs-jgl) < 65536) {
 152           *ofsp = ofs-jgl-32768;
 153           return RID_JGL;
 154         } else {
 155           *ofsp = (int16_t)ofs;
 156           return ra_allock(as, ofs-(int16_t)ofs, allow);
 157         }
 158       }
 159     }
 160   }
 161   *ofsp = 0;
 162   return ra_alloc1(as, ref, allow);
 163 }
 164 
 165 /* Fuse XLOAD/XSTORE reference into load/store operand. */
 166 static void asm_fusexref(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
 167                          RegSet allow, int32_t ofs)
 168 {
 169   IRIns *ir = IR(ref);
 170   Reg base;
 171   if (ra_noreg(ir->r) && canfuse(as, ir)) {
 172     if (ir->o == IR_ADD) {
 173       int32_t ofs2;
 174       if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
 175         ofs = ofs2;
 176         ref = ir->op1;
 177       } else if (ofs == 0) {
 178         Reg right, left = ra_alloc2(as, ir, allow);
 179         right = (left >> 8); left &= 255;
 180         emit_fab(as, PPCI_LWZX | ((pi >> 20) & 0x780), rt, left, right);
 181         return;
 182       }
 183     } else if (ir->o == IR_STRREF) {
 184       lua_assert(ofs == 0);
 185       ofs = (int32_t)sizeof(GCstr);
 186       if (irref_isk(ir->op2)) {
 187         ofs += IR(ir->op2)->i;
 188         ref = ir->op1;
 189       } else if (irref_isk(ir->op1)) {
 190         ofs += IR(ir->op1)->i;
 191         ref = ir->op2;
 192       } else {
 193         /* NYI: Fuse ADD with constant. */
 194         Reg tmp, right, left = ra_alloc2(as, ir, allow);
 195         right = (left >> 8); left &= 255;
 196         tmp = ra_scratch(as, rset_exclude(rset_exclude(allow, left), right));
 197         emit_fai(as, pi, rt, tmp, ofs);
 198         emit_tab(as, PPCI_ADD, tmp, left, right);
 199         return;
 200       }
 201       if (!checki16(ofs)) {
 202         Reg left = ra_alloc1(as, ref, allow);
 203         Reg right = ra_allock(as, ofs, rset_exclude(allow, left));
 204         emit_fab(as, PPCI_LWZX | ((pi >> 20) & 0x780), rt, left, right);
 205         return;
 206       }
 207     }
 208   }
 209   base = ra_alloc1(as, ref, allow);
 210   emit_fai(as, pi, rt, base, ofs);
 211 }
 212 
 213 /* Fuse XLOAD/XSTORE reference into indexed-only load/store operand. */
 214 static void asm_fusexrefx(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
 215                           RegSet allow)
 216 {
 217   IRIns *ira = IR(ref);
 218   Reg right, left;
 219   if (canfuse(as, ira) && ira->o == IR_ADD && ra_noreg(ira->r)) {
 220     left = ra_alloc2(as, ira, allow);
 221     right = (left >> 8); left &= 255;
 222   } else {
 223     right = ra_alloc1(as, ref, allow);
 224     left = RID_R0;
 225   }
 226   emit_tab(as, pi, rt, left, right);
 227 }
 228 
 229 #if !LJ_SOFTFP
 230 /* Fuse to multiply-add/sub instruction. */
 231 static int asm_fusemadd(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pir)
 232 {
 233   IRRef lref = ir->op1, rref = ir->op2;
 234   IRIns *irm;
 235   if (lref != rref &&
 236       ((mayfuse(as, lref) && (irm = IR(lref), irm->o == IR_MUL) &&
 237         ra_noreg(irm->r)) ||
 238        (mayfuse(as, rref) && (irm = IR(rref), irm->o == IR_MUL) &&
 239         (rref = lref, pi = pir, ra_noreg(irm->r))))) {
 240     Reg dest = ra_dest(as, ir, RSET_FPR);
 241     Reg add = ra_alloc1(as, rref, RSET_FPR);
 242     Reg right, left = ra_alloc2(as, irm, rset_exclude(RSET_FPR, add));
 243     right = (left >> 8); left &= 255;
 244     emit_facb(as, pi, dest, left, right, add);
 245     return 1;
 246   }
 247   return 0;
 248 }
 249 #endif
 250 
 251 /* -- Calls --------------------------------------------------------------- */
 252 
 253 /* Generate a call to a C function. */
 254 static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
 255 {
 256   uint32_t n, nargs = CCI_XNARGS(ci);
 257   int32_t ofs = 8;
 258   Reg gpr = REGARG_FIRSTGPR;
 259 #if !LJ_SOFTFP
 260   Reg fpr = REGARG_FIRSTFPR;
 261 #endif
 262   if ((void *)ci->func)
 263     emit_call(as, (void *)ci->func);
 264   for (n = 0; n < nargs; n++) {  /* Setup args. */
 265     IRRef ref = args[n];
 266     if (ref) {
 267       IRIns *ir = IR(ref);
 268 #if !LJ_SOFTFP
 269       if (irt_isfp(ir->t)) {
 270         if (fpr <= REGARG_LASTFPR) {
 271           lua_assert(rset_test(as->freeset, fpr));  /* Already evicted. */
 272           ra_leftov(as, fpr, ref);
 273           fpr++;
 274         } else {
 275           Reg r = ra_alloc1(as, ref, RSET_FPR);
 276           if (irt_isnum(ir->t)) ofs = (ofs + 4) & ~4;
 277           emit_spstore(as, ir, r, ofs);
 278           ofs += irt_isnum(ir->t) ? 8 : 4;
 279         }
 280       } else
 281 #endif
 282       {
 283         if (gpr <= REGARG_LASTGPR) {
 284           lua_assert(rset_test(as->freeset, gpr));  /* Already evicted. */
 285           ra_leftov(as, gpr, ref);
 286           gpr++;
 287         } else {
 288           Reg r = ra_alloc1(as, ref, RSET_GPR);
 289           emit_spstore(as, ir, r, ofs);
 290           ofs += 4;
 291         }
 292       }
 293     } else {
 294       if (gpr <= REGARG_LASTGPR)
 295         gpr++;
 296       else
 297         ofs += 4;
 298     }
 299     checkmclim(as);
 300   }
 301 #if !LJ_SOFTFP
 302   if ((ci->flags & CCI_VARARG))  /* Vararg calls need to know about FPR use. */
 303     emit_tab(as, fpr == REGARG_FIRSTFPR ? PPCI_CRXOR : PPCI_CREQV, 6, 6, 6);
 304 #endif
 305 }
 306 
 307 /* Setup result reg/sp for call. Evict scratch regs. */
 308 static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
 309 {
 310   RegSet drop = RSET_SCRATCH;
 311   int hiop = ((ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t));
 312 #if !LJ_SOFTFP
 313   if ((ci->flags & CCI_NOFPRCLOBBER))
 314     drop &= ~RSET_FPR;
 315 #endif
 316   if (ra_hasreg(ir->r))
 317     rset_clear(drop, ir->r);  /* Dest reg handled below. */
 318   if (hiop && ra_hasreg((ir+1)->r))
 319     rset_clear(drop, (ir+1)->r);  /* Dest reg handled below. */
 320   ra_evictset(as, drop);  /* Evictions must be performed first. */
 321   if (ra_used(ir)) {
 322     lua_assert(!irt_ispri(ir->t));
 323     if (!LJ_SOFTFP && irt_isfp(ir->t)) {
 324       if ((ci->flags & CCI_CASTU64)) {
 325         /* Use spill slot or temp slots. */
 326         int32_t ofs = ir->s ? sps_scale(ir->s) : SPOFS_TMP;
 327         Reg dest = ir->r;
 328         if (ra_hasreg(dest)) {
 329           ra_free(as, dest);
 330           ra_modified(as, dest);
 331           emit_fai(as, PPCI_LFD, dest, RID_SP, ofs);
 332         }
 333         emit_tai(as, PPCI_STW, RID_RETHI, RID_SP, ofs);
 334         emit_tai(as, PPCI_STW, RID_RETLO, RID_SP, ofs+4);
 335       } else {
 336         ra_destreg(as, ir, RID_FPRET);
 337       }
 338 #if LJ_32
 339     } else if (hiop) {
 340       ra_destpair(as, ir);
 341 #endif
 342     } else {
 343       ra_destreg(as, ir, RID_RET);
 344     }
 345   }
 346 }
 347 
 348 static void asm_callx(ASMState *as, IRIns *ir)
 349 {
 350   IRRef args[CCI_NARGS_MAX*2];
 351   CCallInfo ci;
 352   IRRef func;
 353   IRIns *irf;
 354   ci.flags = asm_callx_flags(as, ir);
 355   asm_collectargs(as, ir, &ci, args);
 356   asm_setupresult(as, ir, &ci);
 357   func = ir->op2; irf = IR(func);
 358   if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
 359   if (irref_isk(func)) {  /* Call to constant address. */
 360     ci.func = (ASMFunction)(void *)(intptr_t)(irf->i);
 361   } else {  /* Need a non-argument register for indirect calls. */
 362     RegSet allow = RSET_GPR & ~RSET_RANGE(RID_R0, REGARG_LASTGPR+1);
 363     Reg freg = ra_alloc1(as, func, allow);
 364     *--as->mcp = PPCI_BCTRL;
 365     *--as->mcp = PPCI_MTCTR | PPCF_T(freg);
 366     ci.func = (ASMFunction)(void *)0;
 367   }
 368   asm_gencall(as, &ci, args);
 369 }
 370 
 371 /* -- Returns ------------------------------------------------------------- */
 372 
 373 /* Return to lower frame. Guard that it goes to the right spot. */
 374 static void asm_retf(ASMState *as, IRIns *ir)
 375 {
 376   Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
 377   void *pc = ir_kptr(IR(ir->op2));
 378   int32_t delta = 1+LJ_FR2+bc_a(*((const BCIns *)pc - 1));
 379   as->topslot -= (BCReg)delta;
 380   if ((int32_t)as->topslot < 0) as->topslot = 0;
 381   irt_setmark(IR(REF_BASE)->t);  /* Children must not coalesce with BASE reg. */
 382   emit_setgl(as, base, jit_base);
 383   emit_addptr(as, base, -8*delta);
 384   asm_guardcc(as, CC_NE);
 385   emit_ab(as, PPCI_CMPW, RID_TMP,
 386           ra_allock(as, i32ptr(pc), rset_exclude(RSET_GPR, base)));
 387   emit_tai(as, PPCI_LWZ, RID_TMP, base, -8);
 388 }
 389 
 390 /* -- Type conversions ---------------------------------------------------- */
 391 
 392 #if !LJ_SOFTFP
 393 static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
 394 {
 395   RegSet allow = RSET_FPR;
 396   Reg tmp = ra_scratch(as, rset_clear(allow, left));
 397   Reg fbias = ra_scratch(as, rset_clear(allow, tmp));
 398   Reg dest = ra_dest(as, ir, RSET_GPR);
 399   Reg hibias = ra_allock(as, 0x43300000, rset_exclude(RSET_GPR, dest));
 400   asm_guardcc(as, CC_NE);
 401   emit_fab(as, PPCI_FCMPU, 0, tmp, left);
 402   emit_fab(as, PPCI_FSUB, tmp, tmp, fbias);
 403   emit_fai(as, PPCI_LFD, tmp, RID_SP, SPOFS_TMP);
 404   emit_tai(as, PPCI_STW, RID_TMP, RID_SP, SPOFS_TMPLO);
 405   emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
 406   emit_asi(as, PPCI_XORIS, RID_TMP, dest, 0x8000);
 407   emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
 408   emit_lsptr(as, PPCI_LFS, (fbias & 31),
 409              (void *)&as->J->k32[LJ_K32_2P52_2P31], RSET_GPR);
 410   emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
 411   emit_fb(as, PPCI_FCTIWZ, tmp, left);
 412 }
 413 
 414 static void asm_tobit(ASMState *as, IRIns *ir)
 415 {
 416   RegSet allow = RSET_FPR;
 417   Reg dest = ra_dest(as, ir, RSET_GPR);
 418   Reg left = ra_alloc1(as, ir->op1, allow);
 419   Reg right = ra_alloc1(as, ir->op2, rset_clear(allow, left));
 420   Reg tmp = ra_scratch(as, rset_clear(allow, right));
 421   emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
 422   emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
 423   emit_fab(as, PPCI_FADD, tmp, left, right);
 424 }
 425 #endif
 426 
 427 static void asm_conv(ASMState *as, IRIns *ir)
 428 {
 429   IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
 430 #if !LJ_SOFTFP
 431   int stfp = (st == IRT_NUM || st == IRT_FLOAT);
 432 #endif
 433   IRRef lref = ir->op1;
 434   lua_assert(!(irt_isint64(ir->t) ||
 435                (st == IRT_I64 || st == IRT_U64))); /* Handled by SPLIT. */
 436 #if LJ_SOFTFP
 437   /* FP conversions are handled by SPLIT. */
 438   lua_assert(!irt_isfp(ir->t) && !(st == IRT_NUM || st == IRT_FLOAT));
 439   /* Can't check for same types: SPLIT uses CONV int.int + BXOR for sfp NEG. */
 440 #else
 441   lua_assert(irt_type(ir->t) != st);
 442   if (irt_isfp(ir->t)) {
 443     Reg dest = ra_dest(as, ir, RSET_FPR);
 444     if (stfp) {  /* FP to FP conversion. */
 445       if (st == IRT_NUM)  /* double -> float conversion. */
 446         emit_fb(as, PPCI_FRSP, dest, ra_alloc1(as, lref, RSET_FPR));
 447       else  /* float -> double conversion is a no-op on PPC. */
 448         ra_leftov(as, dest, lref);  /* Do nothing, but may need to move regs. */
 449     } else {  /* Integer to FP conversion. */
 450       /* IRT_INT: Flip hibit, bias with 2^52, subtract 2^52+2^31. */
 451       /* IRT_U32: Bias with 2^52, subtract 2^52. */
 452       RegSet allow = RSET_GPR;
 453       Reg left = ra_alloc1(as, lref, allow);
 454       Reg hibias = ra_allock(as, 0x43300000, rset_clear(allow, left));
 455       Reg fbias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
 456       if (irt_isfloat(ir->t)) emit_fb(as, PPCI_FRSP, dest, dest);
 457       emit_fab(as, PPCI_FSUB, dest, dest, fbias);
 458       emit_fai(as, PPCI_LFD, dest, RID_SP, SPOFS_TMP);
 459       emit_lsptr(as, PPCI_LFS, (fbias & 31),
 460                  &as->J->k32[st == IRT_U32 ? LJ_K32_2P52 : LJ_K32_2P52_2P31],
 461                  rset_clear(allow, hibias));
 462       emit_tai(as, PPCI_STW, st == IRT_U32 ? left : RID_TMP,
 463                RID_SP, SPOFS_TMPLO);
 464       emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
 465       if (st != IRT_U32) emit_asi(as, PPCI_XORIS, RID_TMP, left, 0x8000);
 466     }
 467   } else if (stfp) {  /* FP to integer conversion. */
 468     if (irt_isguard(ir->t)) {
 469       /* Checked conversions are only supported from number to int. */
 470       lua_assert(irt_isint(ir->t) && st == IRT_NUM);
 471       asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
 472     } else {
 473       Reg dest = ra_dest(as, ir, RSET_GPR);
 474       Reg left = ra_alloc1(as, lref, RSET_FPR);
 475       Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
 476       if (irt_isu32(ir->t)) {
 477         /* Convert both x and x-2^31 to int and merge results. */
 478         Reg tmpi = ra_scratch(as, rset_exclude(RSET_GPR, dest));
 479         emit_asb(as, PPCI_OR, dest, dest, tmpi);  /* Select with mask idiom. */
 480         emit_asb(as, PPCI_AND, tmpi, tmpi, RID_TMP);
 481         emit_asb(as, PPCI_ANDC, dest, dest, RID_TMP);
 482         emit_tai(as, PPCI_LWZ, tmpi, RID_SP, SPOFS_TMPLO);  /* tmp = (int)(x) */
 483         emit_tai(as, PPCI_ADDIS, dest, dest, 0x8000);  /* dest += 2^31 */
 484         emit_asb(as, PPCI_SRAWI, RID_TMP, dest, 31);  /* mask = -(dest < 0) */
 485         emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
 486         emit_tai(as, PPCI_LWZ, dest,
 487                  RID_SP, SPOFS_TMPLO);  /* dest = (int)(x-2^31) */
 488         emit_fb(as, PPCI_FCTIWZ, tmp, left);
 489         emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
 490         emit_fb(as, PPCI_FCTIWZ, tmp, tmp);
 491         emit_fab(as, PPCI_FSUB, tmp, left, tmp);
 492         emit_lsptr(as, PPCI_LFS, (tmp & 31),
 493                    (void *)&as->J->k32[LJ_K32_2P31], RSET_GPR);
 494       } else {
 495         emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
 496         emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
 497         emit_fb(as, PPCI_FCTIWZ, tmp, left);
 498       }
 499     }
 500   } else
 501 #endif
 502   {
 503     Reg dest = ra_dest(as, ir, RSET_GPR);
 504     if (st >= IRT_I8 && st <= IRT_U16) {  /* Extend to 32 bit integer. */
 505       Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
 506       lua_assert(irt_isint(ir->t) || irt_isu32(ir->t));
 507       if ((ir->op2 & IRCONV_SEXT))
 508         emit_as(as, st == IRT_I8 ? PPCI_EXTSB : PPCI_EXTSH, dest, left);
 509       else
 510         emit_rot(as, PPCI_RLWINM, dest, left, 0, st == IRT_U8 ? 24 : 16, 31);
 511     } else {  /* 32/64 bit integer conversions. */
 512       /* Only need to handle 32/32 bit no-op (cast) on 32 bit archs. */
 513       ra_leftov(as, dest, lref);  /* Do nothing, but may need to move regs. */
 514     }
 515   }
 516 }
 517 
 518 static void asm_strto(ASMState *as, IRIns *ir)
 519 {
 520   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
 521   IRRef args[2];
 522   int32_t ofs = SPOFS_TMP;
 523 #if LJ_SOFTFP
 524   ra_evictset(as, RSET_SCRATCH);
 525   if (ra_used(ir)) {
 526     if (ra_hasspill(ir->s) && ra_hasspill((ir+1)->s) &&
 527         (ir->s & 1) == LJ_BE && (ir->s ^ 1) == (ir+1)->s) {
 528       int i;
 529       for (i = 0; i < 2; i++) {
 530         Reg r = (ir+i)->r;
 531         if (ra_hasreg(r)) {
 532           ra_free(as, r);
 533           ra_modified(as, r);
 534           emit_spload(as, ir+i, r, sps_scale((ir+i)->s));
 535         }
 536       }
 537       ofs = sps_scale(ir->s & ~1);
 538     } else {
 539       Reg rhi = ra_dest(as, ir+1, RSET_GPR);
 540       Reg rlo = ra_dest(as, ir, rset_exclude(RSET_GPR, rhi));
 541       emit_tai(as, PPCI_LWZ, rhi, RID_SP, ofs);
 542       emit_tai(as, PPCI_LWZ, rlo, RID_SP, ofs+4);
 543     }
 544   }
 545 #else
 546   RegSet drop = RSET_SCRATCH;
 547   if (ra_hasreg(ir->r)) rset_set(drop, ir->r);  /* Spill dest reg (if any). */
 548   ra_evictset(as, drop);
 549   if (ir->s) ofs = sps_scale(ir->s);
 550 #endif
 551   asm_guardcc(as, CC_EQ);
 552   emit_ai(as, PPCI_CMPWI, RID_RET, 0);  /* Test return status. */
 553   args[0] = ir->op1;      /* GCstr *str */
 554   args[1] = ASMREF_TMP1;  /* TValue *n  */
 555   asm_gencall(as, ci, args);
 556   /* Store the result to the spill slot or temp slots. */
 557   emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_SP, ofs);
 558 }
 559 
 560 /* -- Memory references --------------------------------------------------- */
 561 
 562 /* Get pointer to TValue. */
 563 static void asm_tvptr(ASMState *as, Reg dest, IRRef ref)
 564 {
 565   IRIns *ir = IR(ref);
 566   if (irt_isnum(ir->t)) {
 567     if (irref_isk(ref))  /* Use the number constant itself as a TValue. */
 568       ra_allockreg(as, i32ptr(ir_knum(ir)), dest);
 569     else  /* Otherwise force a spill and use the spill slot. */
 570       emit_tai(as, PPCI_ADDI, dest, RID_SP, ra_spill(as, ir));
 571   } else {
 572     /* Otherwise use g->tmptv to hold the TValue. */
 573     RegSet allow = rset_exclude(RSET_GPR, dest);
 574     Reg type;
 575     emit_tai(as, PPCI_ADDI, dest, RID_JGL, (int32_t)offsetof(global_State, tmptv)-32768);
 576     if (!irt_ispri(ir->t)) {
 577       Reg src = ra_alloc1(as, ref, allow);
 578       emit_setgl(as, src, tmptv.gcr);
 579     }
 580     if (LJ_SOFTFP && (ir+1)->o == IR_HIOP)
 581       type = ra_alloc1(as, ref+1, allow);
 582     else
 583       type = ra_allock(as, irt_toitype(ir->t), allow);
 584     emit_setgl(as, type, tmptv.it);
 585   }
 586 }
 587 
 588 static void asm_aref(ASMState *as, IRIns *ir)
 589 {
 590   Reg dest = ra_dest(as, ir, RSET_GPR);
 591   Reg idx, base;
 592   if (irref_isk(ir->op2)) {
 593     IRRef tab = IR(ir->op1)->op1;
 594     int32_t ofs = asm_fuseabase(as, tab);
 595     IRRef refa = ofs ? tab : ir->op1;
 596     ofs += 8*IR(ir->op2)->i;
 597     if (checki16(ofs)) {
 598       base = ra_alloc1(as, refa, RSET_GPR);
 599       emit_tai(as, PPCI_ADDI, dest, base, ofs);
 600       return;
 601     }
 602   }
 603   base = ra_alloc1(as, ir->op1, RSET_GPR);
 604   idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
 605   emit_tab(as, PPCI_ADD, dest, RID_TMP, base);
 606   emit_slwi(as, RID_TMP, idx, 3);
 607 }
 608 
 609 /* Inlined hash lookup. Specialized for key type and for const keys.
 610 ** The equivalent C code is:
 611 **   Node *n = hashkey(t, key);
 612 **   do {
 613 **     if (lj_obj_equal(&n->key, key)) return &n->val;
 614 **   } while ((n = nextnode(n)));
 615 **   return niltv(L);
 616 */
 617 static void asm_href(ASMState *as, IRIns *ir, IROp merge)
 618 {
 619   RegSet allow = RSET_GPR;
 620   int destused = ra_used(ir);
 621   Reg dest = ra_dest(as, ir, allow);
 622   Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
 623   Reg key = RID_NONE, tmp1 = RID_TMP, tmp2;
 624   Reg tisnum = RID_NONE, tmpnum = RID_NONE;
 625   IRRef refkey = ir->op2;
 626   IRIns *irkey = IR(refkey);
 627   int isk = irref_isk(refkey);
 628   IRType1 kt = irkey->t;
 629   uint32_t khash;
 630   MCLabel l_end, l_loop, l_next;
 631 
 632   rset_clear(allow, tab);
 633 #if LJ_SOFTFP
 634   if (!isk) {
 635     key = ra_alloc1(as, refkey, allow);
 636     rset_clear(allow, key);
 637     if (irkey[1].o == IR_HIOP) {
 638       if (ra_hasreg((irkey+1)->r)) {
 639         tmpnum = (irkey+1)->r;
 640         ra_noweak(as, tmpnum);
 641       } else {
 642         tmpnum = ra_allocref(as, refkey+1, allow);
 643       }
 644       rset_clear(allow, tmpnum);
 645     }
 646   }
 647 #else
 648   if (irt_isnum(kt)) {
 649     key = ra_alloc1(as, refkey, RSET_FPR);
 650     tmpnum = ra_scratch(as, rset_exclude(RSET_FPR, key));
 651     tisnum = ra_allock(as, (int32_t)LJ_TISNUM, allow);
 652     rset_clear(allow, tisnum);
 653   } else if (!irt_ispri(kt)) {
 654     key = ra_alloc1(as, refkey, allow);
 655     rset_clear(allow, key);
 656   }
 657 #endif
 658   tmp2 = ra_scratch(as, allow);
 659   rset_clear(allow, tmp2);
 660 
 661   /* Key not found in chain: jump to exit (if merged) or load niltv. */
 662   l_end = emit_label(as);
 663   as->invmcp = NULL;
 664   if (merge == IR_NE)
 665     asm_guardcc(as, CC_EQ);
 666   else if (destused)
 667     emit_loada(as, dest, niltvg(J2G(as->J)));
 668 
 669   /* Follow hash chain until the end. */
 670   l_loop = --as->mcp;
 671   emit_ai(as, PPCI_CMPWI, dest, 0);
 672   emit_tai(as, PPCI_LWZ, dest, dest, (int32_t)offsetof(Node, next));
 673   l_next = emit_label(as);
 674 
 675   /* Type and value comparison. */
 676   if (merge == IR_EQ)
 677     asm_guardcc(as, CC_EQ);
 678   else
 679     emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
 680   if (!LJ_SOFTFP && irt_isnum(kt)) {
 681     emit_fab(as, PPCI_FCMPU, 0, tmpnum, key);
 682     emit_condbranch(as, PPCI_BC, CC_GE, l_next);
 683     emit_ab(as, PPCI_CMPLW, tmp1, tisnum);
 684     emit_fai(as, PPCI_LFD, tmpnum, dest, (int32_t)offsetof(Node, key.n));
 685   } else {
 686     if (!irt_ispri(kt)) {
 687       emit_ab(as, PPCI_CMPW, tmp2, key);
 688       emit_condbranch(as, PPCI_BC, CC_NE, l_next);
 689     }
 690     if (LJ_SOFTFP && ra_hasreg(tmpnum))
 691       emit_ab(as, PPCI_CMPW, tmp1, tmpnum);
 692     else
 693       emit_ai(as, PPCI_CMPWI, tmp1, irt_toitype(irkey->t));
 694     if (!irt_ispri(kt))
 695       emit_tai(as, PPCI_LWZ, tmp2, dest, (int32_t)offsetof(Node, key.gcr));
 696   }
 697   emit_tai(as, PPCI_LWZ, tmp1, dest, (int32_t)offsetof(Node, key.it));
 698   *l_loop = PPCI_BC | PPCF_Y | PPCF_CC(CC_NE) |
 699             (((char *)as->mcp-(char *)l_loop) & 0xffffu);
 700 
 701   /* Load main position relative to tab->node into dest. */
 702   khash = isk ? ir_khash(irkey) : 1;
 703   if (khash == 0) {
 704     emit_tai(as, PPCI_LWZ, dest, tab, (int32_t)offsetof(GCtab, node));
 705   } else {
 706     Reg tmphash = tmp1;
 707     if (isk)
 708       tmphash = ra_allock(as, khash, allow);
 709     emit_tab(as, PPCI_ADD, dest, dest, tmp1);
 710     emit_tai(as, PPCI_MULLI, tmp1, tmp1, sizeof(Node));
 711     emit_asb(as, PPCI_AND, tmp1, tmp2, tmphash);
 712     emit_tai(as, PPCI_LWZ, dest, tab, (int32_t)offsetof(GCtab, node));
 713     emit_tai(as, PPCI_LWZ, tmp2, tab, (int32_t)offsetof(GCtab, hmask));
 714     if (isk) {
 715       /* Nothing to do. */
 716     } else if (irt_isstr(kt)) {
 717       emit_tai(as, PPCI_LWZ, tmp1, key, (int32_t)offsetof(GCstr, hash));
 718     } else {  /* Must match with hash*() in lj_tab.c. */
 719       emit_tab(as, PPCI_SUBF, tmp1, tmp2, tmp1);
 720       emit_rotlwi(as, tmp2, tmp2, HASH_ROT3);
 721       emit_asb(as, PPCI_XOR, tmp1, tmp1, tmp2);
 722       emit_rotlwi(as, tmp1, tmp1, (HASH_ROT2+HASH_ROT1)&31);
 723       emit_tab(as, PPCI_SUBF, tmp2, dest, tmp2);
 724       if (LJ_SOFTFP ? (irkey[1].o == IR_HIOP) : irt_isnum(kt)) {
 725 #if LJ_SOFTFP
 726         emit_asb(as, PPCI_XOR, tmp2, key, tmp1);
 727         emit_rotlwi(as, dest, tmp1, HASH_ROT1);
 728         emit_tab(as, PPCI_ADD, tmp1, tmpnum, tmpnum);
 729 #else
 730         int32_t ofs = ra_spill(as, irkey);
 731         emit_asb(as, PPCI_XOR, tmp2, tmp2, tmp1);
 732         emit_rotlwi(as, dest, tmp1, HASH_ROT1);
 733         emit_tab(as, PPCI_ADD, tmp1, tmp1, tmp1);
 734         emit_tai(as, PPCI_LWZ, tmp2, RID_SP, ofs+4);
 735         emit_tai(as, PPCI_LWZ, tmp1, RID_SP, ofs);
 736 #endif
 737       } else {
 738         emit_asb(as, PPCI_XOR, tmp2, key, tmp1);
 739         emit_rotlwi(as, dest, tmp1, HASH_ROT1);
 740         emit_tai(as, PPCI_ADDI, tmp1, tmp2, HASH_BIAS);
 741         emit_tai(as, PPCI_ADDIS, tmp2, key, (HASH_BIAS + 32768)>>16);
 742       }
 743     }
 744   }
 745 }
 746 
 747 static void asm_hrefk(ASMState *as, IRIns *ir)
 748 {
 749   IRIns *kslot = IR(ir->op2);
 750   IRIns *irkey = IR(kslot->op1);
 751   int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
 752   int32_t kofs = ofs + (int32_t)offsetof(Node, key);
 753   Reg dest = (ra_used(ir)||ofs > 32736) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
 754   Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
 755   Reg key = RID_NONE, type = RID_TMP, idx = node;
 756   RegSet allow = rset_exclude(RSET_GPR, node);
 757   lua_assert(ofs % sizeof(Node) == 0);
 758   if (ofs > 32736) {
 759     idx = dest;
 760     rset_clear(allow, dest);
 761     kofs = (int32_t)offsetof(Node, key);
 762   } else if (ra_hasreg(dest)) {
 763     emit_tai(as, PPCI_ADDI, dest, node, ofs);
 764   }
 765   asm_guardcc(as, CC_NE);
 766   if (!irt_ispri(irkey->t)) {
 767     key = ra_scratch(as, allow);
 768     rset_clear(allow, key);
 769   }
 770   rset_clear(allow, type);
 771   if (irt_isnum(irkey->t)) {
 772     emit_cmpi(as, key, (int32_t)ir_knum(irkey)->u32.lo);
 773     asm_guardcc(as, CC_NE);
 774     emit_cmpi(as, type, (int32_t)ir_knum(irkey)->u32.hi);
 775   } else {
 776     if (ra_hasreg(key)) {
 777       emit_cmpi(as, key, irkey->i);  /* May use RID_TMP, i.e. type. */
 778       asm_guardcc(as, CC_NE);
 779     }
 780     emit_ai(as, PPCI_CMPWI, type, irt_toitype(irkey->t));
 781   }
 782   if (ra_hasreg(key)) emit_tai(as, PPCI_LWZ, key, idx, kofs+4);
 783   emit_tai(as, PPCI_LWZ, type, idx, kofs);
 784   if (ofs > 32736) {
 785     emit_tai(as, PPCI_ADDIS, dest, dest, (ofs + 32768) >> 16);
 786     emit_tai(as, PPCI_ADDI, dest, node, ofs);
 787   }
 788 }
 789 
 790 static void asm_uref(ASMState *as, IRIns *ir)
 791 {
 792   Reg dest = ra_dest(as, ir, RSET_GPR);
 793   if (irref_isk(ir->op1)) {
 794     GCfunc *fn = ir_kfunc(IR(ir->op1));
 795     MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
 796     emit_lsptr(as, PPCI_LWZ, dest, v, RSET_GPR);
 797   } else {
 798     Reg uv = ra_scratch(as, RSET_GPR);
 799     Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
 800     if (ir->o == IR_UREFC) {
 801       asm_guardcc(as, CC_NE);
 802       emit_ai(as, PPCI_CMPWI, RID_TMP, 1);
 803       emit_tai(as, PPCI_ADDI, dest, uv, (int32_t)offsetof(GCupval, tv));
 804       emit_tai(as, PPCI_LBZ, RID_TMP, uv, (int32_t)offsetof(GCupval, closed));
 805     } else {
 806       emit_tai(as, PPCI_LWZ, dest, uv, (int32_t)offsetof(GCupval, v));
 807     }
 808     emit_tai(as, PPCI_LWZ, uv, func,
 809              (int32_t)offsetof(GCfuncL, uvptr) + 4*(int32_t)(ir->op2 >> 8));
 810   }
 811 }
 812 
 813 static void asm_fref(ASMState *as, IRIns *ir)
 814 {
 815   UNUSED(as); UNUSED(ir);
 816   lua_assert(!ra_used(ir));
 817 }
 818 
 819 static void asm_strref(ASMState *as, IRIns *ir)
 820 {
 821   Reg dest = ra_dest(as, ir, RSET_GPR);
 822   IRRef ref = ir->op2, refk = ir->op1;
 823   int32_t ofs = (int32_t)sizeof(GCstr);
 824   Reg r;
 825   if (irref_isk(ref)) {
 826     IRRef tmp = refk; refk = ref; ref = tmp;
 827   } else if (!irref_isk(refk)) {
 828     Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
 829     IRIns *irr = IR(ir->op2);
 830     if (ra_hasreg(irr->r)) {
 831       ra_noweak(as, irr->r);
 832       right = irr->r;
 833     } else if (mayfuse(as, irr->op2) &&
 834                irr->o == IR_ADD && irref_isk(irr->op2) &&
 835                checki16(ofs + IR(irr->op2)->i)) {
 836       ofs += IR(irr->op2)->i;
 837       right = ra_alloc1(as, irr->op1, rset_exclude(RSET_GPR, left));
 838     } else {
 839       right = ra_allocref(as, ir->op2, rset_exclude(RSET_GPR, left));
 840     }
 841     emit_tai(as, PPCI_ADDI, dest, dest, ofs);
 842     emit_tab(as, PPCI_ADD, dest, left, right);
 843     return;
 844   }
 845   r = ra_alloc1(as, ref, RSET_GPR);
 846   ofs += IR(refk)->i;
 847   if (checki16(ofs))
 848     emit_tai(as, PPCI_ADDI, dest, r, ofs);
 849   else
 850     emit_tab(as, PPCI_ADD, dest, r,
 851              ra_allock(as, ofs, rset_exclude(RSET_GPR, r)));
 852 }
 853 
 854 /* -- Loads and stores ---------------------------------------------------- */
 855 
 856 static PPCIns asm_fxloadins(IRIns *ir)
 857 {
 858   switch (irt_type(ir->t)) {
 859   case IRT_I8: return PPCI_LBZ;  /* Needs sign-extension. */
 860   case IRT_U8: return PPCI_LBZ;
 861   case IRT_I16: return PPCI_LHA;
 862   case IRT_U16: return PPCI_LHZ;
 863   case IRT_NUM: lua_assert(!LJ_SOFTFP); return PPCI_LFD;
 864   case IRT_FLOAT: if (!LJ_SOFTFP) return PPCI_LFS;
 865   default: return PPCI_LWZ;
 866   }
 867 }
 868 
 869 static PPCIns asm_fxstoreins(IRIns *ir)
 870 {
 871   switch (irt_type(ir->t)) {
 872   case IRT_I8: case IRT_U8: return PPCI_STB;
 873   case IRT_I16: case IRT_U16: return PPCI_STH;
 874   case IRT_NUM: lua_assert(!LJ_SOFTFP); return PPCI_STFD;
 875   case IRT_FLOAT: if (!LJ_SOFTFP) return PPCI_STFS;
 876   default: return PPCI_STW;
 877   }
 878 }
 879 
 880 static void asm_fload(ASMState *as, IRIns *ir)
 881 {
 882   Reg dest = ra_dest(as, ir, RSET_GPR);
 883   PPCIns pi = asm_fxloadins(ir);
 884   Reg idx;
 885   int32_t ofs;
 886   if (ir->op1 == REF_NIL) {
 887     idx = RID_JGL;
 888     ofs = (ir->op2 << 2) - 32768;
 889   } else {
 890     idx = ra_alloc1(as, ir->op1, RSET_GPR);
 891     if (ir->op2 == IRFL_TAB_ARRAY) {
 892       ofs = asm_fuseabase(as, ir->op1);
 893       if (ofs) {  /* Turn the t->array load into an add for colocated arrays. */
 894         emit_tai(as, PPCI_ADDI, dest, idx, ofs);
 895         return;
 896       }
 897     }
 898     ofs = field_ofs[ir->op2];
 899   }
 900   lua_assert(!irt_isi8(ir->t));
 901   emit_tai(as, pi, dest, idx, ofs);
 902 }
 903 
 904 static void asm_fstore(ASMState *as, IRIns *ir)
 905 {
 906   if (ir->r != RID_SINK) {
 907     Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
 908     IRIns *irf = IR(ir->op1);
 909     Reg idx = ra_alloc1(as, irf->op1, rset_exclude(RSET_GPR, src));
 910     int32_t ofs = field_ofs[irf->op2];
 911     PPCIns pi = asm_fxstoreins(ir);
 912     emit_tai(as, pi, src, idx, ofs);
 913   }
 914 }
 915 
 916 static void asm_xload(ASMState *as, IRIns *ir)
 917 {
 918   Reg dest = ra_dest(as, ir,
 919     (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
 920   lua_assert(!(ir->op2 & IRXLOAD_UNALIGNED));
 921   if (irt_isi8(ir->t))
 922     emit_as(as, PPCI_EXTSB, dest, dest);
 923   asm_fusexref(as, asm_fxloadins(ir), dest, ir->op1, RSET_GPR, 0);
 924 }
 925 
 926 static void asm_xstore_(ASMState *as, IRIns *ir, int32_t ofs)
 927 {
 928   IRIns *irb;
 929   if (ir->r == RID_SINK)
 930     return;
 931   if (ofs == 0 && mayfuse(as, ir->op2) && (irb = IR(ir->op2))->o == IR_BSWAP &&
 932       ra_noreg(irb->r) && (irt_isint(ir->t) || irt_isu32(ir->t))) {
 933     /* Fuse BSWAP with XSTORE to stwbrx. */
 934     Reg src = ra_alloc1(as, irb->op1, RSET_GPR);
 935     asm_fusexrefx(as, PPCI_STWBRX, src, ir->op1, rset_exclude(RSET_GPR, src));
 936   } else {
 937     Reg src = ra_alloc1(as, ir->op2,
 938       (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
 939     asm_fusexref(as, asm_fxstoreins(ir), src, ir->op1,
 940                  rset_exclude(RSET_GPR, src), ofs);
 941   }
 942 }
 943 
 944 #define asm_xstore(as, ir)      asm_xstore_(as, ir, 0)
 945 
 946 static void asm_ahuvload(ASMState *as, IRIns *ir)
 947 {
 948   IRType1 t = ir->t;
 949   Reg dest = RID_NONE, type = RID_TMP, tmp = RID_TMP, idx;
 950   RegSet allow = RSET_GPR;
 951   int32_t ofs = AHUREF_LSX;
 952   if (LJ_SOFTFP && (ir+1)->o == IR_HIOP) {
 953     t.irt = IRT_NUM;
 954     if (ra_used(ir+1)) {
 955       type = ra_dest(as, ir+1, allow);
 956       rset_clear(allow, type);
 957     }
 958     ofs = 0;
 959   }
 960   if (ra_used(ir)) {
 961     lua_assert((LJ_SOFTFP ? 0 : irt_isnum(ir->t)) ||
 962                irt_isint(ir->t) || irt_isaddr(ir->t));
 963     if (LJ_SOFTFP || !irt_isnum(t)) ofs = 0;
 964     dest = ra_dest(as, ir, (!LJ_SOFTFP && irt_isnum(t)) ? RSET_FPR : allow);
 965     rset_clear(allow, dest);
 966   }
 967   idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
 968   if (irt_isnum(t)) {
 969     Reg tisnum = ra_allock(as, (int32_t)LJ_TISNUM, rset_exclude(allow, idx));
 970     asm_guardcc(as, CC_GE);
 971     emit_ab(as, PPCI_CMPLW, type, tisnum);
 972     if (ra_hasreg(dest)) {
 973       if (!LJ_SOFTFP && ofs == AHUREF_LSX) {
 974         tmp = ra_scratch(as, rset_exclude(rset_exclude(RSET_GPR,
 975                                                        (idx&255)), (idx>>8)));
 976         emit_fab(as, PPCI_LFDX, dest, (idx&255), tmp);
 977       } else {
 978         emit_fai(as, LJ_SOFTFP ? PPCI_LWZ : PPCI_LFD, dest, idx,
 979                  ofs+4*LJ_SOFTFP);
 980       }
 981     }
 982   } else {
 983     asm_guardcc(as, CC_NE);
 984     emit_ai(as, PPCI_CMPWI, type, irt_toitype(t));
 985     if (ra_hasreg(dest)) emit_tai(as, PPCI_LWZ, dest, idx, ofs+4);
 986   }
 987   if (ofs == AHUREF_LSX) {
 988     emit_tab(as, PPCI_LWZX, type, (idx&255), tmp);
 989     emit_slwi(as, tmp, (idx>>8), 3);
 990   } else {
 991     emit_tai(as, PPCI_LWZ, type, idx, ofs);
 992   }
 993 }
 994 
 995 static void asm_ahustore(ASMState *as, IRIns *ir)
 996 {
 997   RegSet allow = RSET_GPR;
 998   Reg idx, src = RID_NONE, type = RID_NONE;
 999   int32_t ofs = AHUREF_LSX;
1000   if (ir->r == RID_SINK)
1001     return;
1002   if (!LJ_SOFTFP && irt_isnum(ir->t)) {
1003     src = ra_alloc1(as, ir->op2, RSET_FPR);
1004   } else {
1005     if (!irt_ispri(ir->t)) {
1006       src = ra_alloc1(as, ir->op2, allow);
1007       rset_clear(allow, src);
1008       ofs = 0;
1009     }
1010     if (LJ_SOFTFP && (ir+1)->o == IR_HIOP)
1011       type = ra_alloc1(as, (ir+1)->op2, allow);
1012     else
1013       type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
1014     rset_clear(allow, type);
1015   }
1016   idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
1017   if (!LJ_SOFTFP && irt_isnum(ir->t)) {
1018     if (ofs == AHUREF_LSX) {
1019       emit_fab(as, PPCI_STFDX, src, (idx&255), RID_TMP);
1020       emit_slwi(as, RID_TMP, (idx>>8), 3);
1021     } else {
1022       emit_fai(as, PPCI_STFD, src, idx, ofs);
1023     }
1024   } else {
1025     if (ra_hasreg(src))
1026       emit_tai(as, PPCI_STW, src, idx, ofs+4);
1027     if (ofs == AHUREF_LSX) {
1028       emit_tab(as, PPCI_STWX, type, (idx&255), RID_TMP);
1029       emit_slwi(as, RID_TMP, (idx>>8), 3);
1030     } else {
1031       emit_tai(as, PPCI_STW, type, idx, ofs);
1032     }
1033   }
1034 }
1035 
1036 static void asm_sload(ASMState *as, IRIns *ir)
1037 {
1038   int32_t ofs = 8*((int32_t)ir->op1-1) + ((ir->op2 & IRSLOAD_FRAME) ? 0 : 4);
1039   IRType1 t = ir->t;
1040   Reg dest = RID_NONE, type = RID_NONE, base;
1041   RegSet allow = RSET_GPR;
1042   int hiop = (LJ_SOFTFP && (ir+1)->o == IR_HIOP);
1043   if (hiop)
1044     t.irt = IRT_NUM;
1045   lua_assert(!(ir->op2 & IRSLOAD_PARENT));  /* Handled by asm_head_side(). */
1046   lua_assert(irt_isguard(ir->t) || !(ir->op2 & IRSLOAD_TYPECHECK));
1047   lua_assert(LJ_DUALNUM ||
1048              !irt_isint(t) || (ir->op2 & (IRSLOAD_CONVERT|IRSLOAD_FRAME)));
1049 #if LJ_SOFTFP
1050   lua_assert(!(ir->op2 & IRSLOAD_CONVERT));  /* Handled by LJ_SOFTFP SPLIT. */
1051   if (hiop && ra_used(ir+1)) {
1052     type = ra_dest(as, ir+1, allow);
1053     rset_clear(allow, type);
1054   }
1055 #else
1056   if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t) && irt_isint(t)) {
1057     dest = ra_scratch(as, RSET_FPR);
1058     asm_tointg(as, ir, dest);
1059     t.irt = IRT_NUM;  /* Continue with a regular number type check. */
1060   } else
1061 #endif
1062   if (ra_used(ir)) {
1063     lua_assert(irt_isnum(t) || irt_isint(t) || irt_isaddr(t));
1064     dest = ra_dest(as, ir, (!LJ_SOFTFP && irt_isnum(t)) ? RSET_FPR : allow);
1065     rset_clear(allow, dest);
1066     base = ra_alloc1(as, REF_BASE, allow);
1067     rset_clear(allow, base);
1068     if (!LJ_SOFTFP && (ir->op2 & IRSLOAD_CONVERT)) {
1069       if (irt_isint(t)) {
1070         emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
1071         dest = ra_scratch(as, RSET_FPR);
1072         emit_fai(as, PPCI_STFD, dest, RID_SP, SPOFS_TMP);
1073         emit_fb(as, PPCI_FCTIWZ, dest, dest);
1074         t.irt = IRT_NUM;  /* Check for original type. */
1075       } else {
1076         Reg tmp = ra_scratch(as, allow);
1077         Reg hibias = ra_allock(as, 0x43300000, rset_clear(allow, tmp));
1078         Reg fbias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
1079         emit_fab(as, PPCI_FSUB, dest, dest, fbias);
1080         emit_fai(as, PPCI_LFD, dest, RID_SP, SPOFS_TMP);
1081         emit_lsptr(as, PPCI_LFS, (fbias & 31),
1082                    (void *)&as->J->k32[LJ_K32_2P52_2P31],
1083                    rset_clear(allow, hibias));
1084         emit_tai(as, PPCI_STW, tmp, RID_SP, SPOFS_TMPLO);
1085         emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
1086         emit_asi(as, PPCI_XORIS, tmp, tmp, 0x8000);
1087         dest = tmp;
1088         t.irt = IRT_INT;  /* Check for original type. */
1089       }
1090     }
1091     goto dotypecheck;
1092   }
1093   base = ra_alloc1(as, REF_BASE, allow);
1094   rset_clear(allow, base);
1095 dotypecheck:
1096   if (irt_isnum(t)) {
1097     if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1098       Reg tisnum = ra_allock(as, (int32_t)LJ_TISNUM, allow);
1099       asm_guardcc(as, CC_GE);
1100 #if !LJ_SOFTFP
1101       type = RID_TMP;
1102 #endif
1103       emit_ab(as, PPCI_CMPLW, type, tisnum);
1104     }
1105     if (ra_hasreg(dest)) emit_fai(as, LJ_SOFTFP ? PPCI_LWZ : PPCI_LFD, dest,
1106                                   base, ofs-(LJ_SOFTFP?0:4));
1107   } else {
1108     if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1109       asm_guardcc(as, CC_NE);
1110       emit_ai(as, PPCI_CMPWI, RID_TMP, irt_toitype(t));
1111       type = RID_TMP;
1112     }
1113     if (ra_hasreg(dest)) emit_tai(as, PPCI_LWZ, dest, base, ofs);
1114   }
1115   if (ra_hasreg(type)) emit_tai(as, PPCI_LWZ, type, base, ofs-4);
1116 }
1117 
1118 /* -- Allocations --------------------------------------------------------- */
1119 
1120 #if LJ_HASFFI
1121 static void asm_cnew(ASMState *as, IRIns *ir)
1122 {
1123   CTState *cts = ctype_ctsG(J2G(as->J));
1124   CTypeID id = (CTypeID)IR(ir->op1)->i;
1125   CTSize sz;
1126   CTInfo info = lj_ctype_info(cts, id, &sz);
1127   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
1128   IRRef args[4];
1129   RegSet drop = RSET_SCRATCH;
1130   lua_assert(sz != CTSIZE_INVALID || (ir->o == IR_CNEW && ir->op2 != REF_NIL));
1131 
1132   as->gcsteps++;
1133   if (ra_hasreg(ir->r))
1134     rset_clear(drop, ir->r);  /* Dest reg handled below. */
1135   ra_evictset(as, drop);
1136   if (ra_used(ir))
1137     ra_destreg(as, ir, RID_RET);  /* GCcdata * */
1138 
1139   /* Initialize immutable cdata object. */
1140   if (ir->o == IR_CNEWI) {
1141     RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
1142     int32_t ofs = sizeof(GCcdata);
1143     lua_assert(sz == 4 || sz == 8);
1144     if (sz == 8) {
1145       ofs += 4;
1146       lua_assert((ir+1)->o == IR_HIOP);
1147     }
1148     for (;;) {
1149       Reg r = ra_alloc1(as, ir->op2, allow);
1150       emit_tai(as, PPCI_STW, r, RID_RET, ofs);
1151       rset_clear(allow, r);
1152       if (ofs == sizeof(GCcdata)) break;
1153       ofs -= 4; ir++;
1154     }
1155   } else if (ir->op2 != REF_NIL) {  /* Create VLA/VLS/aligned cdata. */
1156     ci = &lj_ir_callinfo[IRCALL_lj_cdata_newv];
1157     args[0] = ASMREF_L;     /* lua_State *L */
1158     args[1] = ir->op1;      /* CTypeID id   */
1159     args[2] = ir->op2;      /* CTSize sz    */
1160     args[3] = ASMREF_TMP1;  /* CTSize align */
1161     asm_gencall(as, ci, args);
1162     emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)ctype_align(info));
1163     return;
1164   }
1165 
1166   /* Initialize gct and ctypeid. lj_mem_newgco() already sets marked. */
1167   emit_tai(as, PPCI_STB, RID_RET+1, RID_RET, offsetof(GCcdata, gct));
1168   emit_tai(as, PPCI_STH, RID_TMP, RID_RET, offsetof(GCcdata, ctypeid));
1169   emit_ti(as, PPCI_LI, RID_RET+1, ~LJ_TCDATA);
1170   emit_ti(as, PPCI_LI, RID_TMP, id);  /* Lower 16 bit used. Sign-ext ok. */
1171   args[0] = ASMREF_L;     /* lua_State *L */
1172   args[1] = ASMREF_TMP1;  /* MSize size   */
1173   asm_gencall(as, ci, args);
1174   ra_allockreg(as, (int32_t)(sz+sizeof(GCcdata)),
1175                ra_releasetmp(as, ASMREF_TMP1));
1176 }
1177 #else
1178 #define asm_cnew(as, ir)        ((void)0)
1179 #endif
1180 
1181 /* -- Write barriers ------------------------------------------------------ */
1182 
1183 static void asm_tbar(ASMState *as, IRIns *ir)
1184 {
1185   Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
1186   Reg mark = ra_scratch(as, rset_exclude(RSET_GPR, tab));
1187   Reg link = RID_TMP;
1188   MCLabel l_end = emit_label(as);
1189   emit_tai(as, PPCI_STW, link, tab, (int32_t)offsetof(GCtab, gclist));
1190   emit_tai(as, PPCI_STB, mark, tab, (int32_t)offsetof(GCtab, marked));
1191   emit_setgl(as, tab, gc.grayagain);
1192   lua_assert(LJ_GC_BLACK == 0x04);
1193   emit_rot(as, PPCI_RLWINM, mark, mark, 0, 30, 28);  /* Clear black bit. */
1194   emit_getgl(as, link, gc.grayagain);
1195   emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
1196   emit_asi(as, PPCI_ANDIDOT, RID_TMP, mark, LJ_GC_BLACK);
1197   emit_tai(as, PPCI_LBZ, mark, tab, (int32_t)offsetof(GCtab, marked));
1198 }
1199 
1200 static void asm_obar(ASMState *as, IRIns *ir)
1201 {
1202   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
1203   IRRef args[2];
1204   MCLabel l_end;
1205   Reg obj, val, tmp;
1206   /* No need for other object barriers (yet). */
1207   lua_assert(IR(ir->op1)->o == IR_UREFC);
1208   ra_evictset(as, RSET_SCRATCH);
1209   l_end = emit_label(as);
1210   args[0] = ASMREF_TMP1;  /* global_State *g */
1211   args[1] = ir->op1;      /* TValue *tv      */
1212   asm_gencall(as, ci, args);
1213   emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_JGL, -32768);
1214   obj = IR(ir->op1)->r;
1215   tmp = ra_scratch(as, rset_exclude(RSET_GPR, obj));
1216   emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
1217   emit_asi(as, PPCI_ANDIDOT, tmp, tmp, LJ_GC_BLACK);
1218   emit_condbranch(as, PPCI_BC, CC_EQ, l_end);
1219   emit_asi(as, PPCI_ANDIDOT, RID_TMP, RID_TMP, LJ_GC_WHITES);
1220   val = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, obj));
1221   emit_tai(as, PPCI_LBZ, tmp, obj,
1222            (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
1223   emit_tai(as, PPCI_LBZ, RID_TMP, val, (int32_t)offsetof(GChead, marked));
1224 }
1225 
1226 /* -- Arithmetic and logic operations ------------------------------------- */
1227 
1228 #if !LJ_SOFTFP
1229 static void asm_fparith(ASMState *as, IRIns *ir, PPCIns pi)
1230 {
1231   Reg dest = ra_dest(as, ir, RSET_FPR);
1232   Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1233   right = (left >> 8); left &= 255;
1234   if (pi == PPCI_FMUL)
1235     emit_fac(as, pi, dest, left, right);
1236   else
1237     emit_fab(as, pi, dest, left, right);
1238 }
1239 
1240 static void asm_fpunary(ASMState *as, IRIns *ir, PPCIns pi)
1241 {
1242   Reg dest = ra_dest(as, ir, RSET_FPR);
1243   Reg left = ra_hintalloc(as, ir->op1, dest, RSET_FPR);
1244   emit_fb(as, pi, dest, left);
1245 }
1246 
1247 static void asm_fpmath(ASMState *as, IRIns *ir)
1248 {
1249   if (ir->op2 == IRFPM_EXP2 && asm_fpjoin_pow(as, ir))
1250     return;
1251   if (ir->op2 == IRFPM_SQRT && (as->flags & JIT_F_SQRT))
1252     asm_fpunary(as, ir, PPCI_FSQRT);
1253   else
1254     asm_callid(as, ir, IRCALL_lj_vm_floor + ir->op2);
1255 }
1256 #endif
1257 
1258 static void asm_add(ASMState *as, IRIns *ir)
1259 {
1260 #if !LJ_SOFTFP
1261   if (irt_isnum(ir->t)) {
1262     if (!asm_fusemadd(as, ir, PPCI_FMADD, PPCI_FMADD))
1263       asm_fparith(as, ir, PPCI_FADD);
1264   } else
1265 #endif
1266   {
1267     Reg dest = ra_dest(as, ir, RSET_GPR);
1268     Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1269     PPCIns pi;
1270     if (irref_isk(ir->op2)) {
1271       int32_t k = IR(ir->op2)->i;
1272       if (checki16(k)) {
1273         pi = PPCI_ADDI;
1274         /* May fail due to spills/restores above, but simplifies the logic. */
1275         if (as->flagmcp == as->mcp) {
1276           as->flagmcp = NULL;
1277           as->mcp++;
1278           pi = PPCI_ADDICDOT;
1279         }
1280         emit_tai(as, pi, dest, left, k);
1281         return;
1282       } else if ((k & 0xffff) == 0) {
1283         emit_tai(as, PPCI_ADDIS, dest, left, (k >> 16));
1284         return;
1285       } else if (!as->sectref) {
1286         emit_tai(as, PPCI_ADDIS, dest, dest, (k + 32768) >> 16);
1287         emit_tai(as, PPCI_ADDI, dest, left, k);
1288         return;
1289       }
1290     }
1291     pi = PPCI_ADD;
1292     /* May fail due to spills/restores above, but simplifies the logic. */
1293     if (as->flagmcp == as->mcp) {
1294       as->flagmcp = NULL;
1295       as->mcp++;
1296       pi |= PPCF_DOT;
1297     }
1298     right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1299     emit_tab(as, pi, dest, left, right);
1300   }
1301 }
1302 
1303 static void asm_sub(ASMState *as, IRIns *ir)
1304 {
1305 #if !LJ_SOFTFP
1306   if (irt_isnum(ir->t)) {
1307     if (!asm_fusemadd(as, ir, PPCI_FMSUB, PPCI_FNMSUB))
1308       asm_fparith(as, ir, PPCI_FSUB);
1309   } else
1310 #endif
1311   {
1312     PPCIns pi = PPCI_SUBF;
1313     Reg dest = ra_dest(as, ir, RSET_GPR);
1314     Reg left, right;
1315     if (irref_isk(ir->op1)) {
1316       int32_t k = IR(ir->op1)->i;
1317       if (checki16(k)) {
1318         right = ra_alloc1(as, ir->op2, RSET_GPR);
1319         emit_tai(as, PPCI_SUBFIC, dest, right, k);
1320         return;
1321       }
1322     }
1323     /* May fail due to spills/restores above, but simplifies the logic. */
1324     if (as->flagmcp == as->mcp) {
1325       as->flagmcp = NULL;
1326       as->mcp++;
1327       pi |= PPCF_DOT;
1328     }
1329     left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1330     right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1331     emit_tab(as, pi, dest, right, left);  /* Subtract right _from_ left. */
1332   }
1333 }
1334 
1335 static void asm_mul(ASMState *as, IRIns *ir)
1336 {
1337 #if !LJ_SOFTFP
1338   if (irt_isnum(ir->t)) {
1339     asm_fparith(as, ir, PPCI_FMUL);
1340   } else
1341 #endif
1342   {
1343     PPCIns pi = PPCI_MULLW;
1344     Reg dest = ra_dest(as, ir, RSET_GPR);
1345     Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1346     if (irref_isk(ir->op2)) {
1347       int32_t k = IR(ir->op2)->i;
1348       if (checki16(k)) {
1349         emit_tai(as, PPCI_MULLI, dest, left, k);
1350         return;
1351       }
1352     }
1353     /* May fail due to spills/restores above, but simplifies the logic. */
1354     if (as->flagmcp == as->mcp) {
1355       as->flagmcp = NULL;
1356       as->mcp++;
1357       pi |= PPCF_DOT;
1358     }
1359     right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1360     emit_tab(as, pi, dest, left, right);
1361   }
1362 }
1363 
1364 #define asm_div(as, ir)         asm_fparith(as, ir, PPCI_FDIV)
1365 #define asm_mod(as, ir)         asm_callid(as, ir, IRCALL_lj_vm_modi)
1366 #define asm_pow(as, ir)         asm_callid(as, ir, IRCALL_lj_vm_powi)
1367 
1368 static void asm_neg(ASMState *as, IRIns *ir)
1369 {
1370 #if !LJ_SOFTFP
1371   if (irt_isnum(ir->t)) {
1372     asm_fpunary(as, ir, PPCI_FNEG);
1373   } else
1374 #endif
1375   {
1376     Reg dest, left;
1377     PPCIns pi = PPCI_NEG;
1378     if (as->flagmcp == as->mcp) {
1379       as->flagmcp = NULL;
1380       as->mcp++;
1381       pi |= PPCF_DOT;
1382     }
1383     dest = ra_dest(as, ir, RSET_GPR);
1384     left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1385     emit_tab(as, pi, dest, left, 0);
1386   }
1387 }
1388 
1389 #define asm_abs(as, ir)         asm_fpunary(as, ir, PPCI_FABS)
1390 #define asm_atan2(as, ir)       asm_callid(as, ir, IRCALL_atan2)
1391 #define asm_ldexp(as, ir)       asm_callid(as, ir, IRCALL_ldexp)
1392 
1393 static void asm_arithov(ASMState *as, IRIns *ir, PPCIns pi)
1394 {
1395   Reg dest, left, right;
1396   if (as->flagmcp == as->mcp) {
1397     as->flagmcp = NULL;
1398     as->mcp++;
1399   }
1400   asm_guardcc(as, CC_SO);
1401   dest = ra_dest(as, ir, RSET_GPR);
1402   left = ra_alloc2(as, ir, RSET_GPR);
1403   right = (left >> 8); left &= 255;
1404   if (pi == PPCI_SUBFO) { Reg tmp = left; left = right; right = tmp; }
1405   emit_tab(as, pi|PPCF_DOT, dest, left, right);
1406 }
1407 
1408 #define asm_addov(as, ir)       asm_arithov(as, ir, PPCI_ADDO)
1409 #define asm_subov(as, ir)       asm_arithov(as, ir, PPCI_SUBFO)
1410 #define asm_mulov(as, ir)       asm_arithov(as, ir, PPCI_MULLWO)
1411 
1412 #if LJ_HASFFI
1413 static void asm_add64(ASMState *as, IRIns *ir)
1414 {
1415   Reg dest = ra_dest(as, ir, RSET_GPR);
1416   Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
1417   PPCIns pi = PPCI_ADDE;
1418   if (irref_isk(ir->op2)) {
1419     int32_t k = IR(ir->op2)->i;
1420     if (k == 0)
1421       pi = PPCI_ADDZE;
1422     else if (k == -1)
1423       pi = PPCI_ADDME;
1424     else
1425       goto needright;
1426     right = 0;
1427   } else {
1428   needright:
1429     right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1430   }
1431   emit_tab(as, pi, dest, left, right);
1432   ir--;
1433   dest = ra_dest(as, ir, RSET_GPR);
1434   left = ra_alloc1(as, ir->op1, RSET_GPR);
1435   if (irref_isk(ir->op2)) {
1436     int32_t k = IR(ir->op2)->i;
1437     if (checki16(k)) {
1438       emit_tai(as, PPCI_ADDIC, dest, left, k);
1439       return;
1440     }
1441   }
1442   right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1443   emit_tab(as, PPCI_ADDC, dest, left, right);
1444 }
1445 
1446 static void asm_sub64(ASMState *as, IRIns *ir)
1447 {
1448   Reg dest = ra_dest(as, ir, RSET_GPR);
1449   Reg left, right = ra_alloc1(as, ir->op2, RSET_GPR);
1450   PPCIns pi = PPCI_SUBFE;
1451   if (irref_isk(ir->op1)) {
1452     int32_t k = IR(ir->op1)->i;
1453     if (k == 0)
1454       pi = PPCI_SUBFZE;
1455     else if (k == -1)
1456       pi = PPCI_SUBFME;
1457     else
1458       goto needleft;
1459     left = 0;
1460   } else {
1461   needleft:
1462     left = ra_alloc1(as, ir->op1, rset_exclude(RSET_GPR, right));
1463   }
1464   emit_tab(as, pi, dest, right, left);  /* Subtract right _from_ left. */
1465   ir--;
1466   dest = ra_dest(as, ir, RSET_GPR);
1467   right = ra_alloc1(as, ir->op2, RSET_GPR);
1468   if (irref_isk(ir->op1)) {
1469     int32_t k = IR(ir->op1)->i;
1470     if (checki16(k)) {
1471       emit_tai(as, PPCI_SUBFIC, dest, right, k);
1472       return;
1473     }
1474   }
1475   left = ra_alloc1(as, ir->op1, rset_exclude(RSET_GPR, right));
1476   emit_tab(as, PPCI_SUBFC, dest, right, left);
1477 }
1478 
1479 static void asm_neg64(ASMState *as, IRIns *ir)
1480 {
1481   Reg dest = ra_dest(as, ir, RSET_GPR);
1482   Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1483   emit_tab(as, PPCI_SUBFZE, dest, left, 0);
1484   ir--;
1485   dest = ra_dest(as, ir, RSET_GPR);
1486   left = ra_alloc1(as, ir->op1, RSET_GPR);
1487   emit_tai(as, PPCI_SUBFIC, dest, left, 0);
1488 }
1489 #endif
1490 
1491 static void asm_bnot(ASMState *as, IRIns *ir)
1492 {
1493   Reg dest, left, right;
1494   PPCIns pi = PPCI_NOR;
1495   if (as->flagmcp == as->mcp) {
1496     as->flagmcp = NULL;
1497     as->mcp++;
1498     pi |= PPCF_DOT;
1499   }
1500   dest = ra_dest(as, ir, RSET_GPR);
1501   if (mayfuse(as, ir->op1)) {
1502     IRIns *irl = IR(ir->op1);
1503     if (irl->o == IR_BAND)
1504       pi ^= (PPCI_NOR ^ PPCI_NAND);
1505     else if (irl->o == IR_BXOR)
1506       pi ^= (PPCI_NOR ^ PPCI_EQV);
1507     else if (irl->o != IR_BOR)
1508       goto nofuse;
1509     left = ra_hintalloc(as, irl->op1, dest, RSET_GPR);
1510     right = ra_alloc1(as, irl->op2, rset_exclude(RSET_GPR, left));
1511   } else {
1512 nofuse:
1513     left = right = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1514   }
1515   emit_asb(as, pi, dest, left, right);
1516 }
1517 
1518 static void asm_bswap(ASMState *as, IRIns *ir)
1519 {
1520   Reg dest = ra_dest(as, ir, RSET_GPR);
1521   IRIns *irx;
1522   if (mayfuse(as, ir->op1) && (irx = IR(ir->op1))->o == IR_XLOAD &&
1523       ra_noreg(irx->r) && (irt_isint(irx->t) || irt_isu32(irx->t))) {
1524     /* Fuse BSWAP with XLOAD to lwbrx. */
1525     asm_fusexrefx(as, PPCI_LWBRX, dest, irx->op1, RSET_GPR);
1526   } else {
1527     Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1528     Reg tmp = dest;
1529     if (tmp == left) {
1530       tmp = RID_TMP;
1531       emit_mr(as, dest, RID_TMP);
1532     }
1533     emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 16, 23);
1534     emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 0, 7);
1535     emit_rotlwi(as, tmp, left, 8);
1536   }
1537 }
1538 
1539 /* Fuse BAND with contiguous bitmask and a shift to rlwinm. */
1540 static void asm_fuseandsh(ASMState *as, PPCIns pi, int32_t mask, IRRef ref)
1541 {
1542   IRIns *ir;
1543   Reg left;
1544   if (mayfuse(as, ref) && (ir = IR(ref), ra_noreg(ir->r)) &&
1545       irref_isk(ir->op2) && ir->o >= IR_BSHL && ir->o <= IR_BROR) {
1546     int32_t sh = (IR(ir->op2)->i & 31);
1547     switch (ir->o) {
1548     case IR_BSHL:
1549       if ((mask & ((1u<<sh)-1))) goto nofuse;
1550       break;
1551     case IR_BSHR:
1552       if ((mask & ~((~0u)>>sh))) goto nofuse;
1553       sh = ((32-sh)&31);
1554       break;
1555     case IR_BROL:
1556       break;
1557     default:
1558       goto nofuse;
1559     }
1560     left = ra_alloc1(as, ir->op1, RSET_GPR);
1561     *--as->mcp = pi | PPCF_T(left) | PPCF_B(sh);
1562     return;
1563   }
1564 nofuse:
1565   left = ra_alloc1(as, ref, RSET_GPR);
1566   *--as->mcp = pi | PPCF_T(left);
1567 }
1568 
1569 static void asm_band(ASMState *as, IRIns *ir)
1570 {
1571   Reg dest, left, right;
1572   IRRef lref = ir->op1;
1573   PPCIns dot = 0;
1574   IRRef op2;
1575   if (as->flagmcp == as->mcp) {
1576     as->flagmcp = NULL;
1577     as->mcp++;
1578     dot = PPCF_DOT;
1579   }
1580   dest = ra_dest(as, ir, RSET_GPR);
1581   if (irref_isk(ir->op2)) {
1582     int32_t k = IR(ir->op2)->i;
1583     if (k) {
1584       /* First check for a contiguous bitmask as used by rlwinm. */
1585       uint32_t s1 = lj_ffs((uint32_t)k);
1586       uint32_t k1 = ((uint32_t)k >> s1);
1587       if ((k1 & (k1+1)) == 0) {
1588         asm_fuseandsh(as, PPCI_RLWINM|dot | PPCF_A(dest) |
1589                           PPCF_MB(31-lj_fls((uint32_t)k)) | PPCF_ME(31-s1),
1590                           k, lref);
1591         return;
1592       }
1593       if (~(uint32_t)k) {
1594         uint32_t s2 = lj_ffs(~(uint32_t)k);
1595         uint32_t k2 = (~(uint32_t)k >> s2);
1596         if ((k2 & (k2+1)) == 0) {
1597           asm_fuseandsh(as, PPCI_RLWINM|dot | PPCF_A(dest) |
1598                             PPCF_MB(32-s2) | PPCF_ME(30-lj_fls(~(uint32_t)k)),
1599                             k, lref);
1600           return;
1601         }
1602       }
1603     }
1604     if (checku16(k)) {
1605       left = ra_alloc1(as, lref, RSET_GPR);
1606       emit_asi(as, PPCI_ANDIDOT, dest, left, k);
1607       return;
1608     } else if ((k & 0xffff) == 0) {
1609       left = ra_alloc1(as, lref, RSET_GPR);
1610       emit_asi(as, PPCI_ANDISDOT, dest, left, (k >> 16));
1611       return;
1612     }
1613   }
1614   op2 = ir->op2;
1615   if (mayfuse(as, op2) && IR(op2)->o == IR_BNOT && ra_noreg(IR(op2)->r)) {
1616     dot ^= (PPCI_AND ^ PPCI_ANDC);
1617     op2 = IR(op2)->op1;
1618   }
1619   left = ra_hintalloc(as, lref, dest, RSET_GPR);
1620   right = ra_alloc1(as, op2, rset_exclude(RSET_GPR, left));
1621   emit_asb(as, PPCI_AND ^ dot, dest, left, right);
1622 }
1623 
1624 static void asm_bitop(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pik)
1625 {
1626   Reg dest = ra_dest(as, ir, RSET_GPR);
1627   Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1628   if (irref_isk(ir->op2)) {
1629     int32_t k = IR(ir->op2)->i;
1630     Reg tmp = left;
1631     if ((checku16(k) || (k & 0xffff) == 0) || (tmp = dest, !as->sectref)) {
1632       if (!checku16(k)) {
1633         emit_asi(as, pik ^ (PPCI_ORI ^ PPCI_ORIS), dest, tmp, (k >> 16));
1634         if ((k & 0xffff) == 0) return;
1635       }
1636       emit_asi(as, pik, dest, left, k);
1637       return;
1638     }
1639   }
1640   /* May fail due to spills/restores above, but simplifies the logic. */
1641   if (as->flagmcp == as->mcp) {
1642     as->flagmcp = NULL;
1643     as->mcp++;
1644     pi |= PPCF_DOT;
1645   }
1646   right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1647   emit_asb(as, pi, dest, left, right);
1648 }
1649 
1650 #define asm_bor(as, ir)         asm_bitop(as, ir, PPCI_OR, PPCI_ORI)
1651 #define asm_bxor(as, ir)        asm_bitop(as, ir, PPCI_XOR, PPCI_XORI)
1652 
1653 static void asm_bitshift(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pik)
1654 {
1655   Reg dest, left;
1656   Reg dot = 0;
1657   if (as->flagmcp == as->mcp) {
1658     as->flagmcp = NULL;
1659     as->mcp++;
1660     dot = PPCF_DOT;
1661   }
1662   dest = ra_dest(as, ir, RSET_GPR);
1663   left = ra_alloc1(as, ir->op1, RSET_GPR);
1664   if (irref_isk(ir->op2)) {  /* Constant shifts. */
1665     int32_t shift = (IR(ir->op2)->i & 31);
1666     if (pik == 0)  /* SLWI */
1667       emit_rot(as, PPCI_RLWINM|dot, dest, left, shift, 0, 31-shift);
1668     else if (pik == 1)  /* SRWI */
1669       emit_rot(as, PPCI_RLWINM|dot, dest, left, (32-shift)&31, shift, 31);
1670     else
1671       emit_asb(as, pik|dot, dest, left, shift);
1672   } else {
1673     Reg right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1674     emit_asb(as, pi|dot, dest, left, right);
1675   }
1676 }
1677 
1678 #define asm_bshl(as, ir)        asm_bitshift(as, ir, PPCI_SLW, 0)
1679 #define asm_bshr(as, ir)        asm_bitshift(as, ir, PPCI_SRW, 1)
1680 #define asm_bsar(as, ir)        asm_bitshift(as, ir, PPCI_SRAW, PPCI_SRAWI)
1681 #define asm_brol(as, ir) \
1682   asm_bitshift(as, ir, PPCI_RLWNM|PPCF_MB(0)|PPCF_ME(31), \
1683                        PPCI_RLWINM|PPCF_MB(0)|PPCF_ME(31))
1684 #define asm_bror(as, ir)        lua_assert(0)
1685 
1686 #if LJ_SOFTFP
1687 static void asm_sfpmin_max(ASMState *as, IRIns *ir)
1688 {
1689   CCallInfo ci = lj_ir_callinfo[IRCALL_softfp_cmp];
1690   IRRef args[4];
1691   MCLabel l_right, l_end;
1692   Reg desthi = ra_dest(as, ir, RSET_GPR), destlo = ra_dest(as, ir+1, RSET_GPR);
1693   Reg righthi, lefthi = ra_alloc2(as, ir, RSET_GPR);
1694   Reg rightlo, leftlo = ra_alloc2(as, ir+1, RSET_GPR);
1695   PPCCC cond = (IROp)ir->o == IR_MIN ? CC_EQ : CC_NE;
1696   righthi = (lefthi >> 8); lefthi &= 255;
1697   rightlo = (leftlo >> 8); leftlo &= 255;
1698   args[0^LJ_BE] = ir->op1; args[1^LJ_BE] = (ir+1)->op1;
1699   args[2^LJ_BE] = ir->op2; args[3^LJ_BE] = (ir+1)->op2;
1700   l_end = emit_label(as);
1701   if (desthi != righthi) emit_mr(as, desthi, righthi);
1702   if (destlo != rightlo) emit_mr(as, destlo, rightlo);
1703   l_right = emit_label(as);
1704   if (l_end != l_right) emit_jmp(as, l_end);
1705   if (desthi != lefthi) emit_mr(as, desthi, lefthi);
1706   if (destlo != leftlo) emit_mr(as, destlo, leftlo);
1707   if (l_right == as->mcp+1) {
1708     cond ^= 4; l_right = l_end; ++as->mcp;
1709   }
1710   emit_condbranch(as, PPCI_BC, cond, l_right);
1711   ra_evictset(as, RSET_SCRATCH);
1712   emit_cmpi(as, RID_RET, 1);
1713   asm_gencall(as, &ci, args);
1714 }
1715 #endif
1716 
1717 static void asm_min_max(ASMState *as, IRIns *ir, int ismax)
1718 {
1719   if (!LJ_SOFTFP && irt_isnum(ir->t)) {
1720     Reg dest = ra_dest(as, ir, RSET_FPR);
1721     Reg tmp = dest;
1722     Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1723     right = (left >> 8); left &= 255;
1724     if (tmp == left || tmp == right)
1725       tmp = ra_scratch(as, rset_exclude(rset_exclude(rset_exclude(RSET_FPR,
1726                                         dest), left), right));
1727     emit_facb(as, PPCI_FSEL, dest, tmp,
1728               ismax ? left : right, ismax ? right : left);
1729     emit_fab(as, PPCI_FSUB, tmp, left, right);
1730   } else {
1731     Reg dest = ra_dest(as, ir, RSET_GPR);
1732     Reg tmp1 = RID_TMP, tmp2 = dest;
1733     Reg right, left = ra_alloc2(as, ir, RSET_GPR);
1734     right = (left >> 8); left &= 255;
1735     if (tmp2 == left || tmp2 == right)
1736       tmp2 = ra_scratch(as, rset_exclude(rset_exclude(rset_exclude(RSET_GPR,
1737                                          dest), left), right));
1738     emit_tab(as, PPCI_ADD, dest, tmp2, right);
1739     emit_asb(as, ismax ? PPCI_ANDC : PPCI_AND, tmp2, tmp2, tmp1);
1740     emit_tab(as, PPCI_SUBFE, tmp1, tmp1, tmp1);
1741     emit_tab(as, PPCI_SUBFC, tmp2, tmp2, tmp1);
1742     emit_asi(as, PPCI_XORIS, tmp2, right, 0x8000);
1743     emit_asi(as, PPCI_XORIS, tmp1, left, 0x8000);
1744   }
1745 }
1746 
1747 #define asm_min(as, ir)         asm_min_max(as, ir, 0)
1748 #define asm_max(as, ir)         asm_min_max(as, ir, 1)
1749 
1750 /* -- Comparisons --------------------------------------------------------- */
1751 
1752 #define CC_UNSIGNED     0x08    /* Unsigned integer comparison. */
1753 #define CC_TWO          0x80    /* Check two flags for FP comparison. */
1754 
1755 /* Map of comparisons to flags. ORDER IR. */
1756 static const uint8_t asm_compmap[IR_ABC+1] = {
1757   /* op     int cc                 FP cc */
1758   /* LT  */ CC_GE               + (CC_GE<<4),
1759   /* GE  */ CC_LT               + (CC_LE<<4) + CC_TWO,
1760   /* LE  */ CC_GT               + (CC_GE<<4) + CC_TWO,
1761   /* GT  */ CC_LE               + (CC_LE<<4),
1762   /* ULT */ CC_GE + CC_UNSIGNED + (CC_GT<<4) + CC_TWO,
1763   /* UGE */ CC_LT + CC_UNSIGNED + (CC_LT<<4),
1764   /* ULE */ CC_GT + CC_UNSIGNED + (CC_GT<<4),
1765   /* UGT */ CC_LE + CC_UNSIGNED + (CC_LT<<4) + CC_TWO,
1766   /* EQ  */ CC_NE               + (CC_NE<<4),
1767   /* NE  */ CC_EQ               + (CC_EQ<<4),
1768   /* ABC */ CC_LE + CC_UNSIGNED + (CC_LT<<4) + CC_TWO  /* Same as UGT. */
1769 };
1770 
1771 static void asm_intcomp_(ASMState *as, IRRef lref, IRRef rref, Reg cr, PPCCC cc)
1772 {
1773   Reg right, left = ra_alloc1(as, lref, RSET_GPR);
1774   if (irref_isk(rref)) {
1775     int32_t k = IR(rref)->i;
1776     if ((cc & CC_UNSIGNED) == 0) {  /* Signed comparison with constant. */
1777       if (checki16(k)) {
1778         emit_tai(as, PPCI_CMPWI, cr, left, k);
1779         /* Signed comparison with zero and referencing previous ins? */
1780         if (k == 0 && lref == as->curins-1)
1781           as->flagmcp = as->mcp;  /* Allow elimination of the compare. */
1782         return;
1783       } else if ((cc & 3) == (CC_EQ & 3)) {  /* Use CMPLWI for EQ or NE. */
1784         if (checku16(k)) {
1785           emit_tai(as, PPCI_CMPLWI, cr, left, k);
1786           return;
1787         } else if (!as->sectref && ra_noreg(IR(rref)->r)) {
1788           emit_tai(as, PPCI_CMPLWI, cr, RID_TMP, k);
1789           emit_asi(as, PPCI_XORIS, RID_TMP, left, (k >> 16));
1790           return;
1791         }
1792       }
1793     } else {  /* Unsigned comparison with constant. */
1794       if (checku16(k)) {
1795         emit_tai(as, PPCI_CMPLWI, cr, left, k);
1796         return;
1797       }
1798     }
1799   }
1800   right = ra_alloc1(as, rref, rset_exclude(RSET_GPR, left));
1801   emit_tab(as, (cc & CC_UNSIGNED) ? PPCI_CMPLW : PPCI_CMPW, cr, left, right);
1802 }
1803 
1804 static void asm_comp(ASMState *as, IRIns *ir)
1805 {
1806   PPCCC cc = asm_compmap[ir->o];
1807   if (!LJ_SOFTFP && irt_isnum(ir->t)) {
1808     Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1809     right = (left >> 8); left &= 255;
1810     asm_guardcc(as, (cc >> 4));
1811     if ((cc & CC_TWO))
1812       emit_tab(as, PPCI_CROR, ((cc>>4)&3), ((cc>>4)&3), (CC_EQ&3));
1813     emit_fab(as, PPCI_FCMPU, 0, left, right);
1814   } else {
1815     IRRef lref = ir->op1, rref = ir->op2;
1816     if (irref_isk(lref) && !irref_isk(rref)) {
1817       /* Swap constants to the right (only for ABC). */
1818       IRRef tmp = lref; lref = rref; rref = tmp;
1819       if ((cc & 2) == 0) cc ^= 1;  /* LT <-> GT, LE <-> GE */
1820     }
1821     asm_guardcc(as, cc);
1822     asm_intcomp_(as, lref, rref, 0, cc);
1823   }
1824 }
1825 
1826 #define asm_equal(as, ir)       asm_comp(as, ir)
1827 
1828 #if LJ_SOFTFP
1829 /* SFP comparisons. */
1830 static void asm_sfpcomp(ASMState *as, IRIns *ir)
1831 {
1832   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_softfp_cmp];
1833   RegSet drop = RSET_SCRATCH;
1834   Reg r;
1835   IRRef args[4];
1836   args[0^LJ_BE] = ir->op1; args[1^LJ_BE] = (ir+1)->op1;
1837   args[2^LJ_BE] = ir->op2; args[3^LJ_BE] = (ir+1)->op2;
1838 
1839   for (r = REGARG_FIRSTGPR; r <= REGARG_FIRSTGPR+3; r++) {
1840     if (!rset_test(as->freeset, r) &&
1841         regcost_ref(as->cost[r]) == args[r-REGARG_FIRSTGPR])
1842       rset_clear(drop, r);
1843   }
1844   ra_evictset(as, drop);
1845   asm_setupresult(as, ir, ci);
1846   switch ((IROp)ir->o) {
1847   case IR_ULT:
1848     asm_guardcc(as, CC_EQ);
1849     emit_ai(as, PPCI_CMPWI, RID_RET, 0);
1850   case IR_ULE:
1851     asm_guardcc(as, CC_EQ);
1852     emit_ai(as, PPCI_CMPWI, RID_RET, 1);
1853     break;
1854   case IR_GE: case IR_GT:
1855     asm_guardcc(as, CC_EQ);
1856     emit_ai(as, PPCI_CMPWI, RID_RET, 2);
1857   default:
1858     asm_guardcc(as, (asm_compmap[ir->o] & 0xf));
1859     emit_ai(as, PPCI_CMPWI, RID_RET, 0);
1860     break;
1861   }
1862   asm_gencall(as, ci, args);
1863 }
1864 #endif
1865 
1866 #if LJ_HASFFI
1867 /* 64 bit integer comparisons. */
1868 static void asm_comp64(ASMState *as, IRIns *ir)
1869 {
1870   PPCCC cc = asm_compmap[(ir-1)->o];
1871   if ((cc&3) == (CC_EQ&3)) {
1872     asm_guardcc(as, cc);
1873     emit_tab(as, (cc&4) ? PPCI_CRAND : PPCI_CROR,
1874              (CC_EQ&3), (CC_EQ&3), 4+(CC_EQ&3));
1875   } else {
1876     asm_guardcc(as, CC_EQ);
1877     emit_tab(as, PPCI_CROR, (CC_EQ&3), (CC_EQ&3), ((cc^~(cc>>2))&1));
1878     emit_tab(as, (cc&4) ? PPCI_CRAND : PPCI_CRANDC,
1879              (CC_EQ&3), (CC_EQ&3), 4+(cc&3));
1880   }
1881   /* Loword comparison sets cr1 and is unsigned, except for equality. */
1882   asm_intcomp_(as, (ir-1)->op1, (ir-1)->op2, 4,
1883                cc | ((cc&3) == (CC_EQ&3) ? 0 : CC_UNSIGNED));
1884   /* Hiword comparison sets cr0. */
1885   asm_intcomp_(as, ir->op1, ir->op2, 0, cc);
1886   as->flagmcp = NULL;  /* Doesn't work here. */
1887 }
1888 #endif
1889 
1890 /* -- Support for 64 bit ops in 32 bit mode ------------------------------- */
1891 
1892 /* Hiword op of a split 64 bit op. Previous op must be the loword op. */
1893 static void asm_hiop(ASMState *as, IRIns *ir)
1894 {
1895 #if LJ_HASFFI || LJ_SOFTFP
1896   /* HIOP is marked as a store because it needs its own DCE logic. */
1897   int uselo = ra_used(ir-1), usehi = ra_used(ir);  /* Loword/hiword used? */
1898   if (LJ_UNLIKELY(!(as->flags & JIT_F_OPT_DCE))) uselo = usehi = 1;
1899   if ((ir-1)->o == IR_CONV) {  /* Conversions to/from 64 bit. */
1900     as->curins--;  /* Always skip the CONV. */
1901 #if LJ_HASFFI && !LJ_SOFTFP
1902     if (usehi || uselo)
1903       asm_conv64(as, ir);
1904     return;
1905 #endif
1906   } else if ((ir-1)->o <= IR_NE) {  /* 64 bit integer comparisons. ORDER IR. */
1907     as->curins--;  /* Always skip the loword comparison. */
1908 #if LJ_SOFTFP
1909     if (!irt_isint(ir->t)) {
1910       asm_sfpcomp(as, ir-1);
1911       return;
1912     }
1913 #endif
1914 #if LJ_HASFFI
1915     asm_comp64(as, ir);
1916 #endif
1917     return;
1918 #if LJ_SOFTFP
1919   } else if ((ir-1)->o == IR_MIN || (ir-1)->o == IR_MAX) {
1920       as->curins--;  /* Always skip the loword min/max. */
1921     if (uselo || usehi)
1922       asm_sfpmin_max(as, ir-1);
1923     return;
1924 #endif
1925   } else if ((ir-1)->o == IR_XSTORE) {
1926     as->curins--;  /* Handle both stores here. */
1927     if ((ir-1)->r != RID_SINK) {
1928       asm_xstore_(as, ir, 0);
1929       asm_xstore_(as, ir-1, 4);
1930     }
1931     return;
1932   }
1933   if (!usehi) return;  /* Skip unused hiword op for all remaining ops. */
1934   switch ((ir-1)->o) {
1935 #if LJ_HASFFI
1936   case IR_ADD: as->curins--; asm_add64(as, ir); break;
1937   case IR_SUB: as->curins--; asm_sub64(as, ir); break;
1938   case IR_NEG: as->curins--; asm_neg64(as, ir); break;
1939 #endif
1940 #if LJ_SOFTFP
1941   case IR_SLOAD: case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
1942   case IR_STRTO:
1943     if (!uselo)
1944       ra_allocref(as, ir->op1, RSET_GPR);  /* Mark lo op as used. */
1945     break;
1946 #endif
1947   case IR_CALLN:
1948   case IR_CALLS:
1949   case IR_CALLXS:
1950     if (!uselo)
1951       ra_allocref(as, ir->op1, RID2RSET(RID_RETLO));  /* Mark lo op as used. */
1952     break;
1953 #if LJ_SOFTFP
1954   case IR_ASTORE: case IR_HSTORE: case IR_USTORE: case IR_TOSTR:
1955 #endif
1956   case IR_CNEWI:
1957     /* Nothing to do here. Handled by lo op itself. */
1958     break;
1959   default: lua_assert(0); break;
1960   }
1961 #else
1962   UNUSED(as); UNUSED(ir); lua_assert(0);  /* Unused without FFI. */
1963 #endif
1964 }
1965 
1966 /* -- Profiling ----------------------------------------------------------- */
1967 
1968 static void asm_prof(ASMState *as, IRIns *ir)
1969 {
1970   UNUSED(ir);
1971   asm_guardcc(as, CC_NE);
1972   emit_asi(as, PPCI_ANDIDOT, RID_TMP, RID_TMP, HOOK_PROFILE);
1973   emit_lsglptr(as, PPCI_LBZ, RID_TMP,
1974                (int32_t)offsetof(global_State, hookmask));
1975 }
1976 
1977 /* -- Stack handling ------------------------------------------------------ */
1978 
1979 /* Check Lua stack size for overflow. Use exit handler as fallback. */
1980 static void asm_stack_check(ASMState *as, BCReg topslot,
1981                             IRIns *irp, RegSet allow, ExitNo exitno)
1982 {
1983   /* Try to get an unused temp. register, otherwise spill/restore RID_RET*. */
1984   Reg tmp, pbase = irp ? (ra_hasreg(irp->r) ? irp->r : RID_TMP) : RID_BASE;
1985   rset_clear(allow, pbase);
1986   tmp = allow ? rset_pickbot(allow) :
1987                 (pbase == RID_RETHI ? RID_RETLO : RID_RETHI);
1988   emit_condbranch(as, PPCI_BC, CC_LT, asm_exitstub_addr(as, exitno));
1989   if (allow == RSET_EMPTY)  /* Restore temp. register. */
1990     emit_tai(as, PPCI_LWZ, tmp, RID_SP, SPOFS_TMPW);
1991   else
1992     ra_modified(as, tmp);
1993   emit_ai(as, PPCI_CMPLWI, RID_TMP, (int32_t)(8*topslot));
1994   emit_tab(as, PPCI_SUBF, RID_TMP, pbase, tmp);
1995   emit_tai(as, PPCI_LWZ, tmp, tmp, offsetof(lua_State, maxstack));
1996   if (pbase == RID_TMP)
1997     emit_getgl(as, RID_TMP, jit_base);
1998   emit_getgl(as, tmp, cur_L);
1999   if (allow == RSET_EMPTY)  /* Spill temp. register. */
2000     emit_tai(as, PPCI_STW, tmp, RID_SP, SPOFS_TMPW);
2001 }
2002 
2003 /* Restore Lua stack from on-trace state. */
2004 static void asm_stack_restore(ASMState *as, SnapShot *snap)
2005 {
2006   SnapEntry *map = &as->T->snapmap[snap->mapofs];
2007   SnapEntry *flinks = &as->T->snapmap[snap_nextofs(as->T, snap)-1];
2008   MSize n, nent = snap->nent;
2009   /* Store the value of all modified slots to the Lua stack. */
2010   for (n = 0; n < nent; n++) {
2011     SnapEntry sn = map[n];
2012     BCReg s = snap_slot(sn);
2013     int32_t ofs = 8*((int32_t)s-1);
2014     IRRef ref = snap_ref(sn);
2015     IRIns *ir = IR(ref);
2016     if ((sn & SNAP_NORESTORE))
2017       continue;
2018     if (irt_isnum(ir->t)) {
2019 #if LJ_SOFTFP
2020       Reg tmp;
2021       RegSet allow = rset_exclude(RSET_GPR, RID_BASE);
2022       lua_assert(irref_isk(ref));  /* LJ_SOFTFP: must be a number constant. */
2023       tmp = ra_allock(as, (int32_t)ir_knum(ir)->u32.lo, allow);
2024       emit_tai(as, PPCI_STW, tmp, RID_BASE, ofs+(LJ_BE?4:0));
2025       if (rset_test(as->freeset, tmp+1)) allow = RID2RSET(tmp+1);
2026       tmp = ra_allock(as, (int32_t)ir_knum(ir)->u32.hi, allow);
2027       emit_tai(as, PPCI_STW, tmp, RID_BASE, ofs+(LJ_BE?0:4));
2028 #else
2029       Reg src = ra_alloc1(as, ref, RSET_FPR);
2030       emit_fai(as, PPCI_STFD, src, RID_BASE, ofs);
2031 #endif
2032     } else {
2033       Reg type;
2034       RegSet allow = rset_exclude(RSET_GPR, RID_BASE);
2035       lua_assert(irt_ispri(ir->t) || irt_isaddr(ir->t) || irt_isinteger(ir->t));
2036       if (!irt_ispri(ir->t)) {
2037         Reg src = ra_alloc1(as, ref, allow);
2038         rset_clear(allow, src);
2039         emit_tai(as, PPCI_STW, src, RID_BASE, ofs+4);
2040       }
2041       if ((sn & (SNAP_CONT|SNAP_FRAME))) {
2042         if (s == 0) continue;  /* Do not overwrite link to previous frame. */
2043         type = ra_allock(as, (int32_t)(*flinks--), allow);
2044 #if LJ_SOFTFP
2045       } else if ((sn & SNAP_SOFTFPNUM)) {
2046         type = ra_alloc1(as, ref+1, rset_exclude(RSET_GPR, RID_BASE));
2047 #endif
2048       } else {
2049         type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
2050       }
2051       emit_tai(as, PPCI_STW, type, RID_BASE, ofs);
2052     }
2053     checkmclim(as);
2054   }
2055   lua_assert(map + nent == flinks);
2056 }
2057 
2058 /* -- GC handling --------------------------------------------------------- */
2059 
2060 /* Check GC threshold and do one or more GC steps. */
2061 static void asm_gc_check(ASMState *as)
2062 {
2063   const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
2064   IRRef args[2];
2065   MCLabel l_end;
2066   Reg tmp;
2067   ra_evictset(as, RSET_SCRATCH);
2068   l_end = emit_label(as);
2069   /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
2070   asm_guardcc(as, CC_NE);  /* Assumes asm_snap_prep() already done. */
2071   emit_ai(as, PPCI_CMPWI, RID_RET, 0);
2072   args[0] = ASMREF_TMP1;  /* global_State *g */
2073   args[1] = ASMREF_TMP2;  /* MSize steps     */
2074   asm_gencall(as, ci, args);
2075   emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_JGL, -32768);
2076   tmp = ra_releasetmp(as, ASMREF_TMP2);
2077   emit_loadi(as, tmp, as->gcsteps);
2078   /* Jump around GC step if GC total < GC threshold. */
2079   emit_condbranch(as, PPCI_BC|PPCF_Y, CC_LT, l_end);
2080   emit_ab(as, PPCI_CMPLW, RID_TMP, tmp);
2081   emit_getgl(as, tmp, gc.threshold);
2082   emit_getgl(as, RID_TMP, gc.total);
2083   as->gcsteps = 0;
2084   checkmclim(as);
2085 }
2086 
2087 /* -- Loop handling ------------------------------------------------------- */
2088 
2089 /* Fixup the loop branch. */
2090 static void asm_loop_fixup(ASMState *as)
2091 {
2092   MCode *p = as->mctop;
2093   MCode *target = as->mcp;
2094   if (as->loopinv) {  /* Inverted loop branch? */
2095     /* asm_guardcc already inverted the cond branch and patched the final b. */
2096     p[-2] = (p[-2] & (0xffff0000u & ~PPCF_Y)) | (((target-p+2) & 0x3fffu) << 2);
2097   } else {
2098     p[-1] = PPCI_B|(((target-p+1)&0x00ffffffu)<<2);
2099   }
2100 }
2101 
2102 /* -- Head of trace ------------------------------------------------------- */
2103 
2104 /* Coalesce BASE register for a root trace. */
2105 static void asm_head_root_base(ASMState *as)
2106 {
2107   IRIns *ir = IR(REF_BASE);
2108   Reg r = ir->r;
2109   if (ra_hasreg(r)) {
2110     ra_free(as, r);
2111     if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2112       ir->r = RID_INIT;  /* No inheritance for modified BASE register. */
2113     if (r != RID_BASE)
2114       emit_mr(as, r, RID_BASE);
2115   }
2116 }
2117 
2118 /* Coalesce BASE register for a side trace. */
2119 static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
2120 {
2121   IRIns *ir = IR(REF_BASE);
2122   Reg r = ir->r;
2123   if (ra_hasreg(r)) {
2124     ra_free(as, r);
2125     if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2126       ir->r = RID_INIT;  /* No inheritance for modified BASE register. */
2127     if (irp->r == r) {
2128       rset_clear(allow, r);  /* Mark same BASE register as coalesced. */
2129     } else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
2130       rset_clear(allow, irp->r);
2131       emit_mr(as, r, irp->r);  /* Move from coalesced parent reg. */
2132     } else {
2133       emit_getgl(as, r, jit_base);  /* Otherwise reload BASE. */
2134     }
2135   }
2136   return allow;
2137 }
2138 
2139 /* -- Tail of trace ------------------------------------------------------- */
2140 
2141 /* Fixup the tail code. */
2142 static void asm_tail_fixup(ASMState *as, TraceNo lnk)
2143 {
2144   MCode *p = as->mctop;
2145   MCode *target;
2146   int32_t spadj = as->T->spadjust;
2147   if (spadj == 0) {
2148     *--p = PPCI_NOP;
2149     *--p = PPCI_NOP;
2150     as->mctop = p;
2151   } else {
2152     /* Patch stack adjustment. */
2153     lua_assert(checki16(CFRAME_SIZE+spadj));
2154     p[-3] = PPCI_ADDI | PPCF_T(RID_TMP) | PPCF_A(RID_SP) | (CFRAME_SIZE+spadj);
2155     p[-2] = PPCI_STWU | PPCF_T(RID_TMP) | PPCF_A(RID_SP) | spadj;
2156   }
2157   /* Patch exit branch. */
2158   target = lnk ? traceref(as->J, lnk)->mcode : (MCode *)lj_vm_exit_interp;
2159   p[-1] = PPCI_B|(((target-p+1)&0x00ffffffu)<<2);
2160 }
2161 
2162 /* Prepare tail of code. */
2163 static void asm_tail_prep(ASMState *as)
2164 {
2165   MCode *p = as->mctop - 1;  /* Leave room for exit branch. */
2166   if (as->loopref) {
2167     as->invmcp = as->mcp = p;
2168   } else {
2169     as->mcp = p-2;  /* Leave room for stack pointer adjustment. */
2170     as->invmcp = NULL;
2171   }
2172 }
2173 
2174 /* -- Trace setup --------------------------------------------------------- */
2175 
2176 /* Ensure there are enough stack slots for call arguments. */
2177 static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
2178 {
2179   IRRef args[CCI_NARGS_MAX*2];
2180   uint32_t i, nargs = CCI_XNARGS(ci);
2181   int nslots = 2, ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
2182   asm_collectargs(as, ir, ci, args);
2183   for (i = 0; i < nargs; i++)
2184     if (!LJ_SOFTFP && args[i] && irt_isfp(IR(args[i])->t)) {
2185       if (nfpr > 0) nfpr--; else nslots = (nslots+3) & ~1;
2186     } else {
2187       if (ngpr > 0) ngpr--; else nslots++;
2188     }
2189   if (nslots > as->evenspill)  /* Leave room for args in stack slots. */
2190     as->evenspill = nslots;
2191   return (!LJ_SOFTFP && irt_isfp(ir->t)) ? REGSP_HINT(RID_FPRET) :
2192                                            REGSP_HINT(RID_RET);
2193 }
2194 
2195 static void asm_setup_target(ASMState *as)
2196 {
2197   asm_exitstub_setup(as, as->T->nsnap + (as->parent ? 1 : 0));
2198 }
2199 
2200 /* -- Trace patching ------------------------------------------------------ */
2201 
2202 /* Patch exit jumps of existing machine code to a new target. */
2203 void lj_asm_patchexit(jit_State *J, GCtrace *T, ExitNo exitno, MCode *target)
2204 {
2205   MCode *p = T->mcode;
2206   MCode *pe = (MCode *)((char *)p + T->szmcode);
2207   MCode *px = exitstub_trace_addr(T, exitno);
2208   MCode *cstart = NULL;
2209   MCode *mcarea = lj_mcode_patch(J, p, 0);
2210   int clearso = 0;
2211   for (; p < pe; p++) {
2212     /* Look for exitstub branch, try to replace with branch to target. */
2213     uint32_t ins = *p;
2214     if ((ins & 0xfc000000u) == 0x40000000u &&
2215         ((ins ^ ((char *)px-(char *)p)) & 0xffffu) == 0) {
2216       ptrdiff_t delta = (char *)target - (char *)p;
2217       if (((ins >> 16) & 3) == (CC_SO&3)) {
2218         clearso = sizeof(MCode);
2219         delta -= sizeof(MCode);
2220       }
2221       /* Many, but not all short-range branches can be patched directly. */
2222       if (((delta + 0x8000) >> 16) == 0) {
2223         *p = (ins & 0xffdf0000u) | ((uint32_t)delta & 0xffffu) |
2224              ((delta & 0x8000) * (PPCF_Y/0x8000));
2225         if (!cstart) cstart = p;
2226       }
2227     } else if ((ins & 0xfc000000u) == PPCI_B &&
2228                ((ins ^ ((char *)px-(char *)p)) & 0x03ffffffu) == 0) {
2229       ptrdiff_t delta = (char *)target - (char *)p;
2230       lua_assert(((delta + 0x02000000) >> 26) == 0);
2231       *p = PPCI_B | ((uint32_t)delta & 0x03ffffffu);
2232       if (!cstart) cstart = p;
2233     }
2234   }
2235   {  /* Always patch long-range branch in exit stub itself. */
2236     ptrdiff_t delta = (char *)target - (char *)px - clearso;
2237     lua_assert(((delta + 0x02000000) >> 26) == 0);
2238     *px = PPCI_B | ((uint32_t)delta & 0x03ffffffu);
2239   }
2240   if (!cstart) cstart = px;
2241   lj_mcode_sync(cstart, px+1);
2242   if (clearso) {  /* Extend the current trace. Ugly workaround. */
2243     MCode *pp = J->cur.mcode;
2244     J->cur.szmcode += sizeof(MCode);
2245     *--pp = PPCI_MCRXR;  /* Clear SO flag. */
2246     J->cur.mcode = pp;
2247     lj_mcode_sync(pp, pp+1);
2248   }
2249   lj_mcode_patch(J, mcarea, 1);
2250 }
2251 

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